PL613-01 Datasheet, PDF (7/20 Pages) Microchip Technology – 1.8V to 3.3V, PicoPLL, 3-PLL, 200 MHz, 8 Output Clock IC

3.0 FUNCTIONAL DESCRIPTION
The PL613-01 is a highly featured, very flexible,
advanced triple-PLL design for high performance,
low-power applications. The device accepts a low-cost
fundamental crystal input of 10 MHz to 40 MHz or a
reference clock input of 10 MHz to 200 MHz and is
capable of producing eight distinct output frequencies
up to 200 MHz. All three PLLs are fully programmable,
with a total of five, 5-bit post-VCO, odd/even
‘P-counter’ dividers with an additional 1, 2, 4, or 8 ‘Post
P-counter’ dividers that easily generate the most
demanding frequencies. The outputs can be
programmed to deliver the generated frequencies from
the PLLs or the reference input. Each bidirectional
feature pin (I/O) on the PL613-01 incorporates a 60 kΩ
pull-up resistor and can be configured to perform
various functions. Usage of various design features of
these products is mentioned in the following
paragraphs.
3.1 PLL Programming
The three PLLs in PL613-01 are fully programmable.
Each PLL is equipped with an 8-bit input frequency
divider (R-Counter) and an 11-bit VCO frequency
feedback loop (M-Counter) divider. The three PLL
outputs are transferred to five 5-bit post-VCO,
odd/even dividers (P-Counter), as shown in the Block
Diagram. In addition, there are three optional (÷1, ÷2,
÷4, or ÷8) post P-Counter dividers that can further
divide the VCO frequency. In general, the PLL output
frequency is determined by the following formula:
EQUATION 3-1:
F_OUT = F_REF  M  R  P
For output calculations, please note that ‘P’ includes
the P-Counter bits plus the additional optional dividers
(÷1, ÷2, ÷4, or ÷8), if used.
3.2 CLKx (Clock Outputs)
There are a maximum of eight outputs available on the
PL613-01. Clock output frequencies can be configured
as follows:
• CLK[0,3,6]
- F_VCOx / (P*(1, 2, 4, 8))
- F_REF (Crystal or Reference Clock frequency)
- F_REF / (P*(1,2,4,8))
• CLK[1, 7]
- F_VCOx / P
PL613-01
• CLK[2, 4, 5]
- F_VCOx / P
- F_REF
- F_REF / P
Each output can be programmed with a 4 mA, 8 mA, or
16 mA drive strength. The maximum output frequency
is 200 MHz at 3.3V, 166 MHz at 2.5V, or 110 MHz at
1.8V.
3.3 OE (Output Enable)
Four pins can be configured as OE inputs for
controlling individual clock outputs, as show in the table
below.
OEx
Controls Output on
CLK#
OE0
OE2
OE4
OE6
CLK0
CLK2
CLK4
CLK6
Typical enable time is <500 ns plus one clock period.
The OE feature can be programmed to allow the output
to float (HiZ) or to operate in active-low mode. The
programming control for individual OEs is show below.
OE
Pin
OE Type
(Programmable)
Osc PLL Output
0 (default)
On On HiZ
0
1
On
On
Active
0
1
Normal Operation (default)
3.4 OEM (Master Output Enable)
One pin can be configured to be a single Master OE
(OEM) input pin that controls all the outputs of the
PL613-01. In addition, the state of the disabled outputs
can be programmed to float (HiZ) or to operate in
active-low mode. The OEM function operates on the
following logic:
OE
Pin
OE Type
(Programmable)
Osc PLL Output
0 (default)
On On HiZ
0
1
On
On
Active
0
1
Normal Operation (default)
Typical enable time is <500 ns plus one clock period.
 2016 Microchip Technology Inc.
DS20005650A-page 7