TC530 Datasheet, PDF (8/22 Pages) TelCom Semiconductor, Inc – 5V PRECISION DATA ACQUISITION SUBSYSTEMS

TC530/TC534
3.0 DETAILED DESCRIPTION
3.1 Dual Slope Integrating Converter
The TC530/TC534 dual slope converter operates by
integrating the input signal for a fixed time period, then
applying an opposite polarity reference voltage while
timing the period (counting clocks pulses) for the inte-
grator output to cross 0V (deintegrating). The resulting
count is read as conversion data.
A simple mathematical expression that describes dual
slope conversion is:
EQUATION 3-1:
Integrate Voltage = De-integrate Voltage
EQUATION 3-2:
1
R_INTC_INT
∫
T_INT
0
V_IN(T)DT
=
1
R_INTC_INT
∫
T_DEINT
0
V_REF
from which:
EQUATION 3-3:
[ ] [ ] ^(VIN)
(T_INT)
(R_INT)(C_INT)
= (V_REF)
(T_DEINT)
(R_INT)(C_INT)
And therefore:
EQUATION 3-4:
where:
[ ] ^VIN
=
V_REF
T_DEINT
T_INT
V_REF = Reference Voltage
T_INT = Integrate Time
T_DEINT = Reference Voltage De-integrate Time
Inspection of Equation 3-4 shows dual slope converter
accuracy is unrelated to integrating resistor and capac-
itor values, as long as they are stable throughout the
measurement cycle. This measurement technique is
inherently ratiometric (i.e., the ratio between the T_INT
and T_DEINT times is equal to the ratio between V_IN and
V_REF).
Another inherent benefit is noise immunity. Input noise
spikes are integrated, or averaged to zero, during the
integration period. The integrating converter has a noise
immunity with an attenuation rate of at least -20dB per
decade. Interference signals with frequencies at integral
multiples of the integration period are, for the most part,
completely removed. For this reason, the integration
period of the converter is often established to reject 50/
60Hz line noise. The ability to reject such noise is shown
by the plot of Figure 3-1.
In addition to the two phases required for dual slope
measurement (Integrate and De-integrate), the TC530/
TC534 performs two additional adjustments to
minimize measurement error due to system offset volt-
ages. The resulting four internal operations (conver-
sion phases) performed each measurement cycle are:
Auto Zero (AZ), Integrator Output Zero (IZ), Input Inte-
grate (INT) and Reference De-integrate (DINT). The
AZ and IZ phases compensate for system offset errors
and the INT and DINT phases perform the actual A/D
conversion.
FIGURE 3-1:
INTEGRATING
CONVERTER NORMAL
MODE REJECTION
30
T = Measurement
Period
20
10
0
0.1/T
1/T
Input Frequency
10/T
3.2 Auto Zero Phase (AZ)
This phase compensates for errors due to buffer, inte-
grator and comparator offset voltages. During this
phase, an internal feedback loop forces a compensat-
ing error voltage on auto zero capacitor (C_AZ). The
duration of the AZ phase is programmable via the serial
port (see Section 4.1.1, AZ and INT Phase Duration).
DS21433B-page 8
© 2002 Microchip Technology Inc.