PIC18F8720 Datasheet, PDF (8/12 Pages) Microchip Technology – Rev. A4 Silicon/Data Sheet Errata

PIC18F8720/8620/6720/6620
7. Module: Instruction Set (BTG)
In Table 24-1: PIC18FXXXX Instruction Set
(page 262), the BTG instruction has been changed
(change shown in bold text).
TABLE 24-1: PIC18FXXXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
BIT-ORIENTED FILE REGISTER OPERATIONS
BTG
f, b, a Bit Toggle f
1
16-Bit Instruction Word
MSb
LSb
Status
Affected
0111 bbba ffff ffff None
Notes
1, 2
8. Module: OSCCON Register
In the OSCCON register (Register 2-1, page 25),
the Reset value for the SCS bit (OSCCON<0>)
was incorrectly stated as R/W-1 and has been
changed to R/W-0.
9. Module: A/D Converter Characteristics
In Table 26-25: A/D Converter Characteristics
(page 340), specification A40 and Note 6 have
been added:
TABLE 26-25: A/D CONVERTER CHARACTERISTICS: PIC18FXXXX (INDUSTRIAL, EXTENDED)
PIC18LFXX20 (INDUSTRIAL)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
A01 NR
Resolution
—
—
10
bit
A03 EIL
Integral Linearity Error
—
—
<±1
LSb VREF = VDD = 5.0V
A04 EDL
Differential Linearity Error
—
—
<±1
LSb VREF = VDD = 5.0V
A05 EG
Gain Error
—
—
<±1
LSb VREF = VDD = 5.0V
A06 EOFF Offset Error
A10 —
Monotonicity
—
—
<±1.5
guaranteed⁽²⁾
LSb VREF = VDD = 5.0V
— VSS ≤ VAIN ≤ VREF
A20 VREF
A20A
Reference Voltage
(VREFH – VREFL)
1.8V
—
—
V VDD < 3.0V
3V
—
—
V VDD ≥ 3.0V
A21 VREFH Reference Voltage High
A22 VREFL Reference Voltage Low
A25 VAIN
Analog Input Voltage
AVSS
— AVDD + 0.3V V
AVSS – 0.3V⁽⁵⁾ —
VREFH
V
AVSS – 0.3V⁽⁵⁾ — AVDD + 0.3V⁽⁵⁾ V VDD ≥ 2.5V (Note 3)
A30 ZAIN
Recommended Impedance of
—
Analog Voltage Source
—
2.5
kΩ (Note 4)
A40 IAD
A/D Current PIC18FXXXX
—
180
—
μA Average current during
from VDD
PIC18LFXX20
—
90
—
μA ^conversion.
A50 IREF
VREF Input Current (Note 1)
—
—
5
μA During VAIN acquisition.
—
—
150
μA During A/D conversion
cycle.
Note 1:
2:
3:
4:
5:
Vss ≤ VAIN ≤ VREF
The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
For VDD < 2.5V, VAIN should be limited to <.5 VDD.
Maximum allowed impedance for analog voltage source is 10 kΩ. This requires higher acquisition times.
IVDD – AVDDI must be <3.0V and IAVSS – VSSI must be <0.3V.
DS80172C-page 8
© 2005 Microchip Technology Inc.