PIC18F8720 Datasheet, PDF (5/12 Pages) Microchip Technology – Rev. A4 Silicon/Data Sheet Errata

PIC18F8720/8620/6720/6620
2. Module: Timing Diagrams and
Specifications
Table 26-6: External Clock Timing Requirements
for PIC18FX620/X720 devices (page 322) has
been revised (changes and additions are shown in
bold text).
TABLE 26-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
1A
FOSC
External CLKI Frequency⁽¹⁾
DC
25
MHz EC, ECIO oscillator,
PIC18FX620/X720 (Industrial)
Oscillator Frequency⁽¹⁾
DC
16
MHz EC, ECIO oscillator,
PIC18FX620/X720 (Extended)
DC
4
MHz RC oscillator
0.1
4
MHz XT oscillator
4
25
MHz HS oscillator (Industrial)
4
16
MHz HS oscillator (Extended)
4
6.25
MHz HS + PLL oscillator,
PIC18FX620/X720 (Industrial)
4
4
MHz HS + PLL oscillator,
PIC18FX620/X720 (Extended)
1
TOSC
External CLKI Period⁽¹⁾
5
33
kHz LP Oscillator mode
40
—
ns EC, ECIO oscillator,
PIC18FX620/X720 (Industrial)
Oscillator Period⁽¹⁾
62.5
—
ns ^{EC, ECIO oscillator,}
PIC18FX620/X720 (Extended)
250
—
ns RC oscillator
250
10,000
ns XT oscillator
40
250
ns HS oscillator (Industrial)
62.5
250
ns HS oscillator (Extended)
160
250
ns HS + PLL oscillator,
PIC18FX620/X720 (Industrial)
250
250
ns HS + PLL oscillator,
PIC18FX620/X720 (Extended)
30
200
μs LP Oscillator mode
Note 1:
Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All
specified values are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied
to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
3. Module: CCP
In Section 23.3.1 “Wake-up From Sleep”, the list
of peripheral interrupts which can wake the device
from Sleep has been updated. From the list of
11 events, item 4 has been clarified and item 5 has
been removed. The list now reads as follows:
1. PSP read or write.
2. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
3. TMR3 interrupt. Timer3 must be operating as
an asynchronous counter.
4. CCP Capture mode interrupt (Capture will not
occur).
5. MSSP (Start/Stop) bit detect interrupt.
6. MSSP transmit or receive in Slave mode
(SPI/I²C).
7. USART RX or TX (Synchronous Slave mode).
8. A/D conversion (when A/D clock source is RC).
9. EEPROM write operation complete.
10. LVD interrupt.
© 2005 Microchip Technology Inc.
DS80172C-page 5