PIC18F8720 Datasheet, PDF (2/12 Pages) Microchip Technology – Rev. A4 Silicon/Data Sheet Errata

PIC18F8720/8620/6720/6620
5. Module: DAW Instruction
The DAW instruction may improperly clear the
Carry bit (STATUS<0>) when executed.
Work around
Test the Carry bit state before executing the DAW
instruction. If the Carry bit is set, increment the
next higher byte to be added, using an instruction
such as INCFSZ (this instruction does not affect
any Status flags and will not overflow a BCD
nibble). After the DAW instruction has been
executed, process the Carry bit normally (see
Example 1).
EXAMPLE 1:
MOVLW 0x80
ADDLW 0x80
PROCESSING THE CARRY
BIT DURING BCD ADDITIONS
; .80 (BCD)
; .80 (BCD)
BTFSC
INCFSZ
DAW
BTFSC
INCFSZ
STATUS,C
byte2
STATUS,C
byte2
; test C
; inc next higher LSB
; test C
; inc next higher LSB
This is repeated for each DAW instruction
Date Codes that pertain to this issue:
All engineering and production devices.
6. Module: External Memory Interface
(PIC18F8720 and
PIC18F8620 only)
When performing writes on the external memory
interface, a short glitch is present on the LB and
UB lines. The length of the glitch is proportional to
FOSC and also may vary with process, voltage and
temperature. The glitch occurs well before the
WRH line is asserted and no adverse affect on the
operation of the external memory interface has
been observed.
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
7. Module: MSSP (All I²C™ and SPI™ Modes)
The Buffer Full (BF) flag bit of the SSPSTAT regis-
ter (SSPSTAT<0>) may be inadvertently cleared
even when the SSPBUF register has not been
read. This will occur only when the following two
conditions occur simultaneously:
• The four Least Significant bits of the BSR
register are equal to 0Fh (BSR<3:0> = 1111);
and
• Any instruction that contains C9h in its 8 Least
Significant bits (i.e., register file addresses,
literal data, address offsets, etc.) is executed.
Work around
All work arounds will involve setting the contents of
BSR<3:0> to some value other than 0Fh.
In addition to those proposed below, other
solutions may exist.
1. When developing or modifying code, keep
these guidelines in mind:
• Assign 12-bit addresses to all variables.
This allows the assembler to know when
Access Banking can be used.
• Do not set the BSR to point to Bank 15
(BSR = 0Fh).
• Allow the assembler to manipulate the
access bit present in most instructions.
Accessing the SFRs in Bank 15 will be done
through the Access Bank. Continue to use
the BSR to select all GPR Banks.
2. If accessing a part of Bank 15 is required and
the use of Access Banking is not possible,
consider using indirect addressing.
3. If pointing the BSR to Bank 15 is unavoidable,
review the absolute file listing. Verify that no
instructions contain C9h in the 8 Least
Significant bits while the BSR points to Bank 15
(BSR = 0Fh).
Date Codes that pertain to this issue:
All engineering and production devices.
DS80172C-page 2
© 2005 Microchip Technology Inc.