PIC16F818_13 Datasheet, PDF (76/178 Pages) Microchip Technology – 18/20-Pin Enhanced Flash Microcontrollers with nanoWatt Technology

PIC16F818/819
10.3 SSP I²C Mode Operation
The SSP module in I²C mode fully implements all slave
functions, except general call support and provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the standard mode
specifications, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the
RB4/SCK/SCL pin, which is the clock (SCL) and the
RB1/SDI/SDA pin, which is the data (SDA). The user
must configure these pins as inputs or outputs through
the TRISB<4,1> bits.
To ensure proper communication of the I²C Slave mode,
the TRIS bits (TRISx [SDA, SCL]) corresponding to the
I²C pins must be set to ‘1’. If any TRIS bits (TRISx<7:0>)
of the port containing the I²C pins (PORTx [SDA, SCL])
are changed in software during I²C communication
using a Read-Modify-Write instruction (BSF, BCF), then
the I²C mode may stop functioning properly and I²C
communication may suspend. Do not change any of the
TRISx bits (TRIS bits of the port containing the I²C pins)
using the instruction BSF or BCF during I²C communica-
tion. If it is absolutely necessary to change the TRISx
bits during communication, the following method can be
used:
EXAMPLE 10-1:
MOVF
IORLW
ANDLW
TRISC, W
0x18
B’11111001’
MOVWF TRISC
; Example for an 18-pin part such as the PIC16F818/819
; Ensures <4:3> bits are ‘11’
; Sets <2:1> as output, but will not alter other bits
; User can use their own logic here, such as IORLW, XORLW and ANDLW
The SSP module functions are enabled by setting SSP
Enable bit, SSPEN (SSPCON<5>).
FIGURE 10-5:
SSP BLOCK DIAGRAM
(I²C™ MODE)
Read
Internal
Data Bus
Write
RB4/SCK/
SCL
SSPBUF Reg
RB1/
SDI/
SDA
Shift
Clock
SSPSR Reg
MSb
LSb
Match Detect
Addr Match
SSPADD Reg
Start and
Set, Reset
Stop Bit Detect
S, P Bits
(SSPSTAT Reg)
The SSP module has five registers for I²C operation:
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) – Not directly
accessible
• SSP Address Register (SSPADD)
The SSPCON register allows control of the I²C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I²C modes to be selected:
• I²C Slave mode (7-bit address)
• I²C Slave mode (10-bit address)
• I²C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled to support Firmware
Master mode
• I²C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled to support Firmware
Master mode
• I²C Firmware Controlled Master mode with Start
and Stop bit interrupts enabled, slave is Idle
Selection of any I²C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISB bits. Pull-up resistors
must be provided externally to the SCL and SDA pins
for proper operation of the I²C module.
Additional information on SSP I²C operation may be
found in the “PIC^® Mid-Range MCU Family Reference
Manual” (DS33023).
DS39598F-page 76
 2001-2013 Microchip Technology Inc.