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PIC16F818_13 Datasheet, PDF (14/178 Pages) Microchip Technology – 18/20-Pin Enhanced Flash Microcontrollers with nanoWatt Technology | |||
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PIC16F818/819
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Detailson
POR, BOR page:
Bank 1
80h(1) INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
23
81h
82h(1)
83h(1)
84h(1)
85h
OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PCL
Program Counterâs (PC) Least Significant Byte
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
FSR
TRISA
Indirect Data Memory Address Pointer
TRISA7 TRISA6 TRISA5(3) PORTA Data Direction Register (TRISA<4:0>
PS0 1111 1111 17, 54
0000 0000
23
C
0001 1xxx
16
xxxx xxxx
23
1111 1111
39
86h
TRISB
PORTB Data Direction Register
1111 1111
43
87h
â
Unimplemented
â
â
88h
â
Unimplemented
â
â
89h
8Ah(1,2)
8Bh(1)
â
PCLATH
INTCON
Unimplemented
â
â
GIE
PEIE
â
Write Buffer for the upper 5 bits of the PC
TMR0IE
INTE
RBIE
TMR0IF
INTF
â
â
---0 0000
23
RBIF 0000 000x
18
8Ch
PIE1
â
ADIE
â
â
SSPIE
CCP1IE TMR2IE TMR1IE -0-- 0000
19
8Dh
PIE2
â
â
â
EEIE
â
â
â
â
---0 ----
21
8Eh
PCON
â
â
â
â
â
â
POR
BOR ---- --qq
22
8Fh
90h(1)
OSCCON
OSCTUNE
â
IRCF2
IRCF1
IRCF0
â
â
â
TUN5
TUN4
TUN3
IOFS
TUN2
â
TUN1
â
-000 -0--
38
TUN0 --00 0000
36
91h
â
Unimplemented
â
â
92h
PR2
Timer2 Period Register
93h
SSPADD
Synchronous Serial Port (I2C⢠mode) Address Register
1111 1111
0000 0000
68
71, 76
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
72
95h
â
Unimplemented
â
â
96h
â
Unimplemented
â
â
97h
â
Unimplemented
â
â
98h
â
Unimplemented
â
â
99h
â
Unimplemented
â
â
9Ah
â
Unimplemented
â
â
9Bh
â
Unimplemented
â
â
9Ch
â
Unimplemented
â
â
9Dh
â
Unimplemented
â
â
9Eh
ADRESL
A/D Result Register Low Byte
xxxx xxxx
81
9Fh
ADCON1
ADFM ADCS2
â
â
PCFG3 PCFG2 PCFG1
PCFG0 00-- 0000
82
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as â0â, r = reserved.
Shaded locations are unimplemented, read as â0â.
These registers can be addressed from any bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read â1â.
DS39598F-page 14
ï£ 2001-2013 Microchip Technology Inc.
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