PIC16F818_13 Datasheet, PDF (138/178 Pages) Microchip Technology – 18/20-Pin Enhanced Flash Microcontrollers with nanoWatt Technology

PIC16F818/819
TABLE 15-8: I²C™ BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100* THIGH Clock High Time 100 kHz mode
4.0
—
s
400 kHz mode
0.6
—
s
SSP Module
1.5 TCY
—
101* TLOW
Clock Low Time 100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
SSP Module
1.5 TCY
—
102* TR
SDA and SCL Rise 100 kHz mode
—
1000
Time
400 kHz mode 20 + 0.1 CB 300
ns
ns CB is specified to be from
10-400 pF
103* TF
SDA and SCL Fall 100 kHz mode
—
300
Time
400 kHz mode 20 + 0.1 CB 300
ns
ns CB is specified to be from
10-400 pF
90*
TSU:STA Start Condition
100 kHz mode
4.7
—
s Only relevant for Repeated
Setup Time
400 kHz mode
0.6
—
s ^{Start condition}
91*
THD:STA Start Condition Hold 100 kHz mode
4.0
—
s After this period, the first
Time
400 kHz mode
0.6
—
s ^{clock pulse is generated}
106*
THD:DAT Data Input Hold
Time
100 kHz mode
400 kHz mode
0
—
ns
0
0.9 s
107* TSU:DAT Data Input Setup 100 kHz mode
250
—
ns (Note 2)
Time
400 kHz mode
100
—
ns
92*
TSU:STO Stop Condition
100 kHz mode
4.7
—
s
Setup Time
400 kHz mode
0.6
—
s
109* TAA
Output Valid from 100 kHz mode
Clock
400 kHz mode
—
3500 ns (Note 1)
—
—
ns
110* TBUF
Bus Free Time
100 kHz mode
4.7
—
s Time the bus must be free
400 kHz mode
1.3
—
s ^{before a new transmission}
can start
CB
Bus Capacitive Loading
—
400 pF
* These parameters are characterized but not tested.
Note 1:
2:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode (400 kHz) I²C™ bus device can be used in a Standard mode (100 kHz) I²C bus system but
the requirement, TSU:DAT 250 ns, must then be met. This will automatically be the case if the device does
not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL
signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns
(according to the Standard mode I²C bus specification), before the SCL line is released.
DS39598F-page 138
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