24C01SC_04 Datasheet, PDF (7/16 Pages) Microchip Technology – 1K/2K 5.0V I2C Serial EEPROMs for Smart Cards

5.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then NO ACK will be
returned. If the cycle is complete, then the device will
return the ACK, and the master can then proceed with
the next Read or Write command. See Figure 5-1 for
flow diagram.
FIGURE 5-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
NO
(ACK = 0)?
YES
Next
Operation
24C01SC/24C02SC
6.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
6.1 Current Address Read
The 24C01SC/02SC contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to address
n, the next current address read operation would
access data from address n + 1. Upon receipt of the
slave address with R/W bit set to one, the 24C01SC/
02SC issues an acknowledge and transmits the 8-bit
data word. The master will not acknowledge the transfer
but does generate a Stop condition and the 24C01SC/
02SC discontinues transmission (Figure 6-1).
6.2 Random Read
Random read operations allow the master to access any
memory location in a random manner. To perform this
type of read operation, first the word address must be
set. This is done by sending the word address to the
24C01SC/02SC as part of a write operation. After the
word address is sent, the master generates a Start
condition following the acknowledge. This terminates
the write operation, but not before the internal address
pointer is set. Then, the master issues the control byte
again but with the R/W bit set to a one. The 24C01SC/
02SC will then issue an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer but does generate a Stop condition and the
24C01SC/02SC discontinues transmission (Figure 6-2).
6.3 Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24C01SC/02SC
transmits the first data byte, the master issues an
acknowledge as opposed to a Stop condition in a
random read. This directs the 24C01SC/02SC to
transmit the next sequentially addressed 8-bit word
(Figure 6-3).
To provide sequential reads the 24C01SC/02SC
contains an internal address pointer which is incre-
mented by one at the completion of each operation.
This address pointer allows the entire memory contents
to be serially read during one operation.
 2004 Microchip Technology Inc.
DS21170E-page 7