24C01SC_04 Datasheet, PDF (3/16 Pages) Microchip Technology – 1K/2K 5.0V I2C Serial EEPROMs for Smart Cards

24C01SC/24C02SC
TABLE 1-2: AC CHARACTERISTICS
Parameter
Symbol
Min.
Max. Units
Remarks
Clock frequency
FCLK
—
400
kHz
Clock high time
THIGH
600
—
ns
Clock low time
TLOW
1300
—
ns
SDA and SCL rise time
TR
—
300
ns (Note 1)
SDA and SCL fall time
TF
—
300
ns (Note 1)
Start condition hold time
THD:STA
600
—
ns After this period the first clock
pulse is generated
Start condition setup time
TSU:STA
600
—
ns Only relevant for repeated
Start condition
Data input hold time
THD:DAT
0
—
ns (Note 2)
Data input setup time
TSU:DAT
100
—
ns
Stop condition setup time
TSU:STO
600
—
ns
Output valid from clock
TAA
—
900
ns (Note 2)
Bus free time
TBUF
1300
—
ns Time the bus must be free
before a new transmission can
start
Output fall time from VIH
minimum to VIL maximum
TOF
20 + 0.1 250
CB
ns (Note 1), CB = 100 pF
Input filter spike suppression
(SDA and SCL pins)
TSP
—
50
ns (Note 3)
Write cycle time
TWR
—
10
ms Byte or Page mode
Endurance
—
1M
—
cycles 25°C, Vcc = 5V, Block mode
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance^™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
FIGURE 1-2:
BUS TIMING DATA
TF
TR
THIGH
TLOW
SCL
TSU:STA
SDA
IN
TSP
THD:STA
THD:DAT
TSU:DAT TSU:STO
SDA
OUT
TAA
THD:STA
TAA
TBUF
 2004 Microchip Technology Inc.
DS21170E-page 3