SST89E516RD2_13 Datasheet, PDF (65/94 Pages) Microchip Technology – FlashFlex MCU

FlashFlex MCU
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
Reset
Data Sheet
A system reset initializes the MCU and begins program execution at program memory location 0000H.
The reset input for the device is the RST pin. In order to reset the device, a logic level high must be
applied to the RST pin for at least two machine cycles (24 clocks), after the oscillator becomes stable.
ALE, PSEN# are weakly pulled high during reset. During reset, ALE and PSEN# output a high level in
order to perform a proper reset. This level must not be affected by external element. A system reset will
not affect the 1 KByte of on-chip RAM while the device is running, however, the contents of the on-chip
RAM during power up are indeterminate. Following reset, all Special Function Registers (SFR) return
to their reset values outlined in Tables 6 to 10.
Power-on Reset
At initial power up, the port pins will be in a random state until the oscillator has started and the internal
reset algorithm has weakly pulled all pins high. Powering up the device without a valid reset could
cause the MCU to start executing instructions from an indeterminate location. Such undefined
states may inadvertently corrupt the code in the flash.
When power is applied to the device, the RST pin must be held high long enough for the oscillator to start up (usu-
ally several milliseconds for a low frequency crystal), in addition to two machine cycles for a valid power-on reset. An
example of a method to extend the RST signal is to implement a RC circuit by connecting the RST pin to V_DD
through a 10 µF capacitor and to V_SS through an 8.2KΩ resistor as shown in Figure 31. Note that if an RC circuit is
being used, provisions should be made to ensure the V_DD rise time does not exceed 1 millisecond and the oscillator
start-up time does not exceed 10 milliseconds.
For a low frequency oscillator with slow start-up time the reset signal must be extended in order to
account for the slow start-up time. This method maintains the necessary relationship between V_DD and
RST to avoid programming at an indeterminate location, which may cause corruption in the code of the
flash. The power-on detection is designed to work as power up initially, before the voltage reaches the
brown-out detection level. The POF flag in the PCON register is set to indicate an initial power up con-
dition. The POF flag will remain active until cleared by software. Please see Section , “Power Control
Register (PCON)” on page 31 for detailed information.
For more information on system level design techniques, please review the FlashFlex MCU: Oscilla-
tor Circuit Design Considerations application note.
V_DD
+
10µF
-
8.2K
C₂
C₁
Figure 31:Power-on Reset Circuit
RST
V_DD
SST89E/V516RDx
XTAL2
XTAL1
1273 F27.0
©2013 Silicon Storage Technology, Inc.
65
DS25093B
02/13