COM20020ILJP Datasheet, PDF (65/72 Pages) Microchip Technology – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
XTAL1
4.0V
t1
t2
1.0V
t3
50% of VDD
Parameter
t1
Input Clock High Time
t2
Input Clock Low Time
t3
Input Clock Period
t4
Input Clock Frequency
t5
Frequency Accuracy*
min typ max units
10
nS
10
nS
25
100 ^nS
10
40 MHz
-200
200 ppm
Note*: Input clock frequency must be 20 MHz (+- 100ppm or better) to use the internal Clock Multiplier.
t5 is applied to crystal oscillaton.
Figure 8.13 - TTL Input Timing on XTAL1 Pin
t1
nRESET
nINTR
t2
Parameter
min typ
t1
nRESET Pulse Width***
t2
nINTR High to Next nINTR Low EF = 0
EF = 1
5TXTL^*
TDR**/2
4TXTL*
Note*: TXTL is period of external XTAL oscillation frequency.
Note**: TDR is period of Data Rate (i.e. at 2.5 Mbps, TDR = 400 nS)
Note***: When the power is turned on, t1 is measured from stable XTAL
oscillation after VDD was over 4.5V.
max units
Figure 8.14 - Reset and Interrupt Timing
SMSC COM20020I Rev D
Page 65
DATASHEET
Revision 12-05-06