COM20020ILJP Datasheet, PDF (27/72 Pages) Microchip Technology – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
Note 6.1 (R/W) This bit can be Written or Read. For more information see Appendix C -
Identification of the COM20020 Rev B, Rev C and Rev D.
Software
Table 6.2 - Write Register Summary
ADDR MSB
00 RI/TR1
0
0
01
C7
C6
C5
02
RD-
AUTO-
0
DATA
INC
03
A7
A6
A5
WRITE
0
EXCNAK
C4
C3
0
0
RECON
C2
A10
NEW
NEXTID
C1
A9
LSB
TA/
TTA
C0
A8
A4
A3
A2
A1
A0
04
05
06
07-0
07-1
07-2
07-3
07-4
D7
D6
D5
D4
(R/W)
0
0
0
Note 6.2
RESET CCHEN TXEN
ET1
TID7
NID7
P1-
MODE
0
RBUS-
TMG
TID6
NID6
FOUR
NAKS
0
0
TID5
NID5
0
0
CKUP1
TID4
NID4
RCV-
ALL
0
CKUP0
D3
(R/W)
Note 6.2
ET2
TID3
NID3
CKP3
0
EF
D2
SUB-
AD2
BACK-
PLANE
TID2
NID2
CKP2
0
NO-
SYNC
D1
SUB-
AD1
SUB-
AD1
TID1
NID1
CKP1
0
RCN-
TM1
D0
SUB-
AD0
SUB-
AD0
TID0
NID0
SLOW-
ARB
0
RCN-
TM0
REGISTER
INTERRUPT
MASK
COMMAND
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
DATA
SUBADR
CONFIG-
URATION
TENTID
NODEID
SETUP1
TEST
SETUP2
Note 6.2 (R/W) This bit can be Written or Read. For more information see Appendix C -
Identification of the COM20020 Rev B, Rev C and Rev D.
Software
6.2
Internal Registers
The COM20020ID contains 14 internal registers. Table 6.1 and Table 6.2 illustrate the COM20020ID
register map. All undefined bits are read as undefined and must be written as logic "0".
6.2.1 Interrupt Mask Register (IMR)
The COM20020ID is capable of generating an interrupt signal when certain status bits become true. A
write to the IMR specifies which status bits will be enabled to generate an interrupt. The bit positions in the
IMR are in the same position as their corresponding status bits in the Status Register and Diagnostic
Status Register. A logic "1" in a particular position enables the corresponding interrupt. The Status bits
capable of generating an interrupt include the Receiver Inhibited bit, New Next ID bit, Excessive NAK bit,
Reconfiguration Timer bit, and Transmitter Available bit. No other Status or Diagnostic Status bits can
generate an interrupt.
The six maskable status bits are ANDed with their respective mask bits, and the results are ORed to
produce the interrupt signal. An RI or TA interrupt is masked when the corresponding mask bit is reset
to logic "0", but will reappear when the corresponding mask bit is set to logic "1" again, unless the interrupt
status condition has been cleared by this time. A RECON interrupt is cleared when the "Clear Flags"
command is issued. An EXCNAK interrupt is cleared when the "POR Clear Flags" command is issued. A
SMSC COM20020I Rev D
Page 27
DATASHEET
Revision 12-05-06