COM20020ILJP Datasheet, PDF (34/72 Pages) Microchip Technology – 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
BIT
BIT NAME
7 Read Data
6 Auto Increment
5-3 (Reserved)
2-0 Address 10-8
Table 6.6 - Address Pointer High Register
SYMBOL
RDDATA
AUTOINC
A10-A8
DESCRIPTION
This bit tells the COM20020ID whether the following access will
be a read or write. A logic "1" prepares the device for a read, a
logic "0" prepares it for a write.
This bit controls whether the address pointer will increment
automatically. A logic "1" on this bit allows automatic increment of
the pointer after each access, while a logic "0" disables this
function. Please refer to the Sequential Access Memory section
for further detail.
These bits are undefined.
These bits hold the upper three address bits which provide
addresses to RAM.
BIT
BIT NAME
7-0 Address 7-0
Table 6.7 - Address Pointer Low Register
SYMBOL
A7-A0
DESCRIPTION
These bits hold the lower 8 address bits which provide the
addresses to RAM.
BIT
7-3
2,1,0
BIT NAME
Reserved
Sub Address 2,1,0
Table 6.8 - Sub Address Register
SYMBOL
SUBAD
2,1,0
DESCRIPTION
These bits are undefined.
These bits determine which register at address 07 may be
accessed. The combinations are as follows:
SUBAD2 SUBAD1 SUBAD0
Register
0
0
0
Tentative ID \ (Same
0
0
1
Node ID
\ as in
0
1
0
Setup 1
/ Config
0
1
1
Next ID
/ Register)
1
0
0
Setup 2
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
SUBAD1 and SUBAD0 are exactly the same as exist in the
Configuration Register. SUBAD2 is cleared automatically by writing
the Configuration Register.
Revision 12-05-06
Page 34
DATASHEET
SMSC COM20020I Rev D