SST39VF6401B Datasheet, PDF (6/36 Pages) Silicon Storage Technology, Inc – 64 Mbit (x16) Multi-Purpose Flash Plus

64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Device Operation
Not Recommended for New Designs
Commands are used to initiate the memory operation functions of the device. Commands are written
to the device using standard microprocessor write sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
The SST39VF640xB also have the Auto Low Power mode which puts the device in a near standby
mode after data has been accessed with a valid Read operation. This reduces the I_DD active read cur-
rent from typically 9 mA to typically 3 µA. The Auto Low Power mode reduces the typical I_DD active
read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power mode
with any address transition or control signal transition used to initiate another Read cycle, with no
access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with
CE# held steadily low, until the first address transition or CE# is driven high.
Read
The Read operation of the SST39VF640xB is controlled by CE# and OE#, both have to be low for the
system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is
deselected and only standby power is consumed. OE# is the output control and is used to gate data
from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to
the Read cycle timing diagram for further details (Figure 3).
Word-Program Operation
The SST39VF640xB are programmed on a word-by-word basis. Before programming, the sector
where the word exists must be fully erased. The Program operation is accomplished in three steps.
The first step is the three-byte load sequence for Software Data Protection. The second step is to load
word address and word data. During the Word-Program operation, the addresses are latched on the
falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of
either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is ini-
tiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation,
once initiated, will be completed within 10 µs. See Figures 4 and 5 for WE# and CE# controlled Pro-
gram operation timing diagrams and Figure 19 for flowcharts. During the Program operation, the only
valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to
perform additional tasks. Any commands issued during the internal Program operation are ignored.
During the command sequence, WP# should be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or
block-by-block) basis. The SST39VF640xB offer both Sector-Erase and Block-Erase mode. The sector
architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform
block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command
sequence with Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The Block-
Erase operation is initiated by executing a six-byte command sequence with Block-Erase command
(30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling
edge of the sixth WE# pulse, while the command (50H or 30H) is latched on the rising edge of the sixth
WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase opera-
tion can be determined using either Data# Polling or Toggle Bit methods. See Figures 9 and 10 for tim-
© 2015
DS20005008B
08/15
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