24LC09_04 Datasheet, PDF (6/18 Pages) Microchip Technology – 8K 2.5V ACR SERIAL EEPROM

24LC09
4.3 Stop Data Transfer (C)
A low to high transition of the SDA line while the clock
(SCL) is high determines a stop condition. All opera-
tions must be ended with a stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a start condition and
terminated with a stop condition. The number of the
data bytes transferred between the start and stop con-
ditions is determined by the master device and is theo-
retically unlimited, although only the last 16 will be
stored when doing a write operation. When an over-
write does occur, it will replace data in a first in first out
fashion.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24LC09 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the stop condition.
4.6 Device Addressing
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a 4-bit control code, for the 24LC09 this is
set as 1011 binary for read and write operations. The
next three bits of the control byte are the block select
bits (B2, B1, B0). B2 is a don't care for the 24LC09.
They are used by the master device to select which of
the four 256 word blocks of memory are to be
accessed. These bits are in effect the most significant
bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24LC09 monitors the
SDA bus checking the device type identifier being
transmitted, upon a 1011 code the slave device out-
puts an acknowledge signal on the SDA line. Depend-
ing on the state of the R/W bit, the 24LC09 will select a
read or write operation.
Operation
Control
Code
Block Select
R/W
Read
1011
Block Address
1
Write
1011
Block Address
0
FIGURE 4-2:
CONTROL BYTE
ALLOCATION
START
READ/WRITE
SLAVE ADDRESS
R/W A
1 0 1 1 X B1 B0
X = Don’t care.
DS21675B-page 6
 2004 Microchip Technology Inc.