24LC09_04 Datasheet, PDF (5/18 Pages) Microchip Technology – 8K 2.5V ACR SERIAL EEPROM

24LC09
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Name
VSS
SDA
SCL
WP
VCC
A0, A1, A2
Function
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+2.5V to 5.5V Power Supply
No Internal Connection
2.1 Serial Address/Data Input/Output
(SDA)
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
2.2 Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
2.3 Write Protect (WP)
This pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory).
If tied to VCC, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
This feature allows the user to use the 24LC09 as a
serial ROM when WP is enabled (tied to VCC).
2.4 A0, A1, A2
These pins are not used by the 24LC09. They may be
left floating or tied to either VSS or VCC.
3.0 FUNCTIONAL DESCRIPTION
The 24LC09 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus has to be con-
trolled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the Start and Stop conditions, while the 24LC09 works
as slave. Both, master and slave can operate as trans-
mitter or receiver but the master device determines
which mode is activated.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a start or stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus not Busy (A)
Both data and clock lines remain High.
4.2 Start Data Transfer (B)
A High to Low transition of the SDA line while the clock
(SCL) is high determines a start condition. All com-
mands must be preceded by a start condition.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
SCL
(C) (A)
SDA
START
CONDITION
ADDRESS OR
DATA
ACKNOWLEDGE ALLOWED
VALID
TO CHANGE
STOP
CONDITION
 2004 Microchip Technology Inc.
DS21675B-page 5