PIC24FJ256GA705 Datasheet, PDF (5/10 Pages) –

PIC24FJ256GA705 FAMILY
EXAMPLE 2: USING POSC WHEN WAKING FROM SLEEP
// Clock Switching Enabled (Failsafe Clock Monitor can be enabled or disabled)
#pragma config FCKSM = CSECMD
----------------------------------------------
// switch to FRC = 0 before entering sleep
__builtin_write_OSCCONH(0);
__builtin_write_OSCCONL(1);
while(OSCCONbits.OSWEN == 1);
// wait for switch
// enter sleep mode
Sleep();
// configure REFO to request POSC
REFOCONLbits.ROSEL = 2;
// POSC
REFOCONLbits.ROOUT = 0;
// disable output
REFOCONLbits.ROEN = 1;
// enable module
// wait for POSC stable clock
// this delay may vary depending on different application conditions
// such as voltage, temperature, layout, XT or HS mode and components
{ // delay for 9 ms
unsigned int delayms = 9;
while(delayms--) asm volatile("repeat #(8000000/1000/2) \n nop");
}
// switch to POSC = 2
__builtin_write_OSCCONH(2);
__builtin_write_OSCCONL(1);
while(OSCCONbits.OSWEN == 1);
// wait for switch
Affected Silicon Revisions
A3
X
5. Module: Power
When the device wakes up from Retention Sleep
mode (RETEN bit (RCON<12>) = 1, LPCFG bit
(FPOR<2>) = 0), occasionally a device reset may
occur. The BOR, POR and EXTR bits in the
RCON register are set erroneously for this Reset.
Work around
To provide a consistent behavior when the device
wakes up from Retention Sleep mode, a software
RESET instruction (RESET) should be inserted
following the SLEEP instruction. In this case, a
Reset will be always be generated when the
device wakes up from Retention Sleep.
Example 3 shows the software RESET instruction
implementation:
EXAMPLE 3: SOFTWARE RESET AFTER
SLEEP INSTRUCTION
// ENTER SLEEP MODE.
asm volatile (“pwrsav #0”);
// SOFTWARE RESET RIGHT AFTER SLEEP.
asm volatile(“reset”);
Affected Silicon Revisions
A3
X
 2016 Microchip Technology Inc.
DS80000718B-page 5