PIC24FJ256GA705 Datasheet, PDF (2/10 Pages) –

PIC24FJ256GA705 FAMILY
TABLE 2: SILICON ISSUE SUMMARY
Module
Feature
Item
Number
Issue Summary
Affected
Revisions⁽¹⁾
A3
I²C
Address Hold 1. In Slave mode when AHEN = 1 (Address Hold Enable), if
X
ACKDT (Acknowledge Data bit) is set at the beginning of
address reception, clock stretching will not happen after the
8th clock.
Reset
I²C
Trap Conflict
2. The TRAPR bit is not getting set when a hard trap conflict
X
occurs.
Data Hold
3. In Slave mode when DHEN = 1 (Data Hold Enable), if
X
ACKDT (Acknowledge Data bit) is set at the beginning of
data reception, then a slave interrupt will not occur after the
8th clock.
Primary XT Primary
4. OST may indicate oscillator is ready for use too early.
X
and HS
Oscillator
Oscillator
Start-up
(POSC)
Timer (OST)
Power
Retention
Sleep
5. When the device wakes up from Retention Sleep mode
X
(RETEN bit (RCON<12>) = 1, LPCFG bit (FPOR<2>) = 0), a
device Reset may occur. The BOR, POR and EXTR bits in
the RCON register are set erroneously for this Reset.
Note 1: Only those issues indicated in the last column apply to the current silicon revision.
DS80000718B-page 2
 2016 Microchip Technology Inc.