PIC24FJ256GA705 Datasheet, PDF (3/10 Pages) –

PIC24FJ256GA705 FAMILY
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A3).
1. Module: I²C
In Slave mode when AHEN = 1 (Address Hold
Enable), if the ACKDT bit (Acknowledge Data) is
set at the beginning of address reception, clock
stretching will not happen after the 8th clock.
Work around
In Slave mode, user software should clear
ACKDT on receiving the Start bit.
Affected Silicon Revisions
A3
X
3. Module: I²C
In Slave mode when DHEN = 1 (Data Hold
Enable), if the ACKDT bit (Acknowledge Data) is
set at the beginning of data reception, then the
slave interrupt will not occur after the 8th clock.
Work around
In Slave mode, user software should clear
ACKDT on receiving the Start bit.
Affected Silicon Revisions
A3
X
2. Module: Reset
If a lower priority address error trap occurs while
a higher priority oscillator failure trap is being
processed, the TRAPR bit (RCON<15>) is not
set. A Trap Conflict Reset does not occur as
expected and the device may stop executing
code.
Work around
None. However, a MCLR/POR Reset will
recover the device.
Affected Silicon Revisions
A3
X
 2016 Microchip Technology Inc.
DS80000718B-page 3