PIC24FJ128GA010 Datasheet, PDF (5/10 Pages) Microchip Technology – PIC24FJ128GA010 Family Rev. A4 Silicon Errata

22. Module: I²C™
During I²C Slave mode transactions, the Data/
Address bit, D/A, may not update during the data
frame. This affects both 7 and 10-Bit Addressing
modes.
I²C slave receptions are not affected by this issue.
Work around
Use the Read/Write bit, R/W, and the Transmit
Buffer Full Status Bit, TBF, to determine whether
address or data information is being received.
For more information, see Figure 24-30 and
Figure 24-31 in “Section 24. Inter-Integrated
Circuit™ (I²C™)” (DS39702A).
Date Codes that pertain to this issue:
All engineering and production devices.
23. Module: I²C
When the I²C module is operating in Slave mode,
after the ACKSTAT bit is set when receiving a
NACK from the master, it may be cleared by the
reception of a Start or Stop bit.
Work around
Store the value of the ACKSTAT bit immediately
after receiving a NACK from the master.
Date Codes that pertain to this issue:
All engineering and production devices.
24. Module: UART
When an auto-baud is detected, the receive inter-
rupt may occur twice. The first interrupt occurs at
the beginning of the Start bit and the second after
reception of the Sync field character.
Work around
If a receive interrupt occurs, check the URXDA bit
(UxSTA<0>) to ensure that valid data is available.
On the first interrupt, no data will be present. The
second interrupt will have the Sync field character
(55h) in the receive FIFO.
Date Codes that pertain to this issue:
All engineering and production devices.
PIC24FJ128GA010
25. Module: UART
The auto-baud may miscalculate for certain baud
rates and clock speed combinations, resulting in a
BRG value that is 1 greater or less than the
expected value. When UxBRG is less than 50, this
can result in transmission and reception failures
due to introducing error greater than 1%.
Work around
Test auto-baud calculations at various clock speed
and baud rate combinations that would be used in
applications. If an inaccurate UxBRG value is
generated, manually correct the baud rate in user
code.
Date Codes that pertain to this issue:
All engineering and production devices.
26. Module: UART
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
This issue does not affect the other UART
configurations.
Work around
Use the 16x baud rate option (BRGH = 0) and
adjust the baud rate accordingly.
Date Codes that pertain to this issue:
All engineering and production devices.
27. Module: SPI
In SPI Master mode, the Disable SCK Pin bit,
DISSCK, may not disable the SPI clock. As a
result, the PIC^® microcontroller must provide the
SPI clock in Master mode.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
© 2007 Microchip Technology Inc.
DS80330A-page 5