PIC24FJ128GA010 Datasheet, PDF (2/10 Pages) Microchip Technology – PIC24FJ128GA010 Family Rev. A4 Silicon Errata

PIC24FJ128GA010
5. Module: Output Compare
The output compare module may output a single
glitch for one TCY after the module is enabled
(OCM<2:0> = 000). This issue occurs when the
output state of the associated Data Latch register
(LATx) is in the opposite state of the Output Com-
pare mode when the peripheral is enabled. It can
also occur when switching between two Output
Compare modes with opposite output states.
Work around
If the output glitch must be avoided, verify that the
associated data latch value of the OCx pin matches
the initial state of the desired Output Compare
mode. For example, if Output Compare 5 is config-
ured for mode, OCM<2:0> = 001, ensure that the
LATD<4> bit is clear prior to writing the OCM bits.
The port latch output value will match the initial out-
put state of the OC5 pin and avoid the glitch when
the peripheral is enabled.
Date Codes that pertain to this issue:
All engineering and production devices.
6. Module: UART
The timing for transmitting a Sync Break has
changed for this revision of silicon. The Sync
Break is transmitted as soon as the UTXBRK bit is
set. A dummy write to UxTXREG is still required
and must be performed before the Sync Break has
finished transmitting. Otherwise, the UxTX may be
held in the active state until the write has occurred.
Work around
Set the UTXBRK bit when a Sync Break is
required and perform a dummy UxTXREG imme-
diately following. This sequence will avoid holding
the UxTX pin in the active state.
Date Codes that pertain to this issue:
All engineering and production devices.
7. Module: UART
When the UART is in High-Speed mode, BRGH
(UxMODE<3>) is set, some optimal UxBRG
values can cause reception to fail.
Work around
Test UxBRG values in the application to find a
UxBRG value that works consistently for more
high-speed applications. User should verify that
the UxBRG baud rate error does not exceed the
application limits.
Date Codes that pertain to this issue:
All engineering and production devices.
8. Module: UART
UART1 and UART2 hardware flow control options
are not available for the 64-pin variants of the
PIC24FJ128GA010 product family. As a result, the
UxCTS and UxRTS pins not available and the
UEN<1:0> control bits are read as ‘0’ (unimple-
mented). UART2 hardware flow control is not
available for the 80-pin PIC24FJ128GA010
variants. Therefore associated pins and bits are
not available for these devices.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
9. Module: UART
When the UART is in High-Speed mode
(BRGH = 1), the auto-baud sequence can calculate
the baud rate as if it were in Low-Speed mode.
Work around
The calculated baud rate can be modified by the
following equation:
New BRG Value = (Auto-Baud BRG + 1) * 4 – 1
The user should verify baud rate error does not
exceed application limits.
Date Codes that pertain to this issue:
All engineering and production devices.
10. Module: UART
With the auto-baud feature selected, the Sync
Break character (0x55) may be loaded into the
FIFO as data.
Work around
To prevent the Sync Break character from being
loaded into the FIFO, load the UxBRG register with
either 0x0000 or 0xFFFF prior to enabling the
auto-baud feature (ABAUD = 1).
Date Codes that pertain to this issue:
All engineering and production devices.
DS80330A-page 2
© 2007 Microchip Technology Inc.