PIC24FJ128GA010 Datasheet, PDF (3/10 Pages) Microchip Technology – PIC24FJ128GA010 Family Rev. A4 Silicon Errata

11. Module: A/D
Gain error may be as high as 5 LSbs for external
references (VREF+ and VREF-) and 6 LSbs for
internal reference (AVDD and AVSS).
Work around
Determine gain error from a known reference
voltage and compensate the A/D result in
software.
Date Codes that pertain to this issue:
All engineering and production devices.
12. Module: A/D
With the External Interrupt 0 (INT0) selected to start
an A/D conversion (SSRC<2:0> = 001), the device
may not wake-up from Sleep or Idle mode if more
than one conversion is selected per interrupt
(SMPI<3:0> <> 0000). Interrupts are generated
correctly if the device is not in a Sleep or Idle mode.
Work around
Configure the A/D to generate an interrupt after
every conversion (SMPI<3:0> = 0000). Use
another wake-up source, such as the WDT or
another interrupt source, to exit the Sleep or Idle
mode. Alternatively, perform A/D conversions in
Run mode.
Date Codes that pertain to this issue:
All engineering and production devices.
13. Module: SPI
The Enhanced SPI modes, selected by setting the
Enhanced Buffer Enable bit, SPIBEN
(SPIxCON2<0>), are not available.
Work around
Use Standard SPI mode by clearing the SPI
Enhanced Buffer Enable bit, SPIBEN.
Date Codes that pertain to this issue:
All engineering and production devices.
PIC24FJ128GA010
14. Module: SPI
Master mode receptions using the SPI1 and SPI2
modules may not function correctly for bit rates
above 8 Mbps if the master has the SMP bit
(SPIxCON1<9>) cleared (master samples data at
the middle of the serial clock period).
In this case, the data transmitted by the slave is
received, shifted right by one bit, by the master.
For example, if the data transmitted by the slave
was 0xAAAA, the data received by the master
would be 0x5555 (0xAAAA shifted right by one bit).
Work around
Users may set up the SPI module so that the bit
rate is 8 Mbps or lower.
Alternatively, the bit rate can be configured higher
than 8 Mbps, but the SMP bit (SPIxCON1<9>) of
the SPI master must be set (master samples data
at the end of the serial clock period).
Date Codes that pertain to this issue:
All engineering and production devices.
15. Module: SPI
A frame synchronization pulse may not be output
in SPI Master mode if the pulse is selected to
coincide with the first bit clock (SPIFE = 1). SCKx
and SDOx waveforms are not affected.
Work around
Select the frame sychronization pulses to proceed
the first bit clock (SPIFE = 0). The frame pulses
will output correctly as described in the product
data sheet.
Date Codes that pertain to this issue:
All engineering and production devices.
© 2007 Microchip Technology Inc.
DS80330A-page 3