24LC08B Datasheet, PDF (5/12 Pages) Microchip Technology – 8K/16K I 2 C ™ Serial EEPROMs in ISO Micromodules

24LC08B/16B MODULES
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24LC08B/16B does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by NOT generating an acknowledge
bit on the last byte that has been clocked out of the
slave. In this case, the slave (24LC08B/16B) will leave
the data line HIGH to enable the master to generate the
STOP condition.
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a 4-bit control code, for the 24LC08B/16B
this is set as 1010 binary for read and write operations.
The next three bits of the control byte are the block
select bits (B2, B1, B0). They are used by the master
device to select which of the eight 256 word blocks of
memory are to be accessed. These bits are in effect the
three most significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24LC08B/16B moni-
tors the SDA bus checking the device type identifier
being transmitted, upon a 1010 code the slave device
outputs an acknowledge signal on the SDA line.
Depending on the state of the R/W bit, the 24LC08B/
16B will select a read or write operation.
Operation
Read
Write
Control
Code
1010
1010
Block Select R/W
Block Address 1
Block Address 0
FIGURE 5-1:
START
CONTROL BYTE
ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W A
1
0
1
0
B2 B1 B0
FIGURE 5-2: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A) (B)
(D)
(D)
SCL
SDA
START
CONDITION
ADDRESS OR
DATA
ACKNOWLEDGE ALLOWED
VALID
TO CHANGE
(C) (A)
STOP
CONDITION
© 1997 Microchip Technology Inc.
DS21224A-page 5