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24LC08B Datasheet, PDF (3/12 Pages) Microchip Technology – 8K/16K I 2 C ™ Serial EEPROMs in ISO Micromodules | |||
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24LC08B/16B MODULES
TABLE 1-3 AC CHARACTERISTICS
All parameters apply across the speciï¬ed operat- Vcc = 2.5V to 5.5V
ing ranges unless otherwise noted.
Commercial (C):
Tamb = 0°C to +70°C
Parameter
Vcc = 2.5V - 5.5V Vcc = 4.5V - 5.5V
Symbol STD MODE
FAST MODE Units
Remarks
Min. Max. Min. Max.
Clock frequency
FCLK
â
100
â
400 kHz
Clock high time
THIGH 4000
â
600
â
ns
Clock low time
TLOW 4700
â
1300
â
ns
SDA and SCL rise time
TR
â
1000
â
300 ns (Note 1)
SDA and SCL fall time
TF
â
300
â
300 ns (Note 1)
START condition hold time THD:STA 4000
â
600
â
ns After this period the ï¬rst
clock pulse is generated
START condition setup time TSU:STA 4700
â
600
â
ns Only relevant for repeated
START condition
Data input hold time
THD:DAT
0
â
0
â
ns (Note 2)
Data input setup time
TSU:DAT 250
â
100
â
ns
STOP condition setup time TSU:STO 4000
â
600
â
ns
Output valid from clock
TAA
â
3500
â
900 ns (Note 2)
Bus free time
TBUF 4700
â
1300
â
ns Time the bus must be free
before a new transmission
can start
Output fall time from VIH
TOF
minimum to VIL maximum
Input ï¬lter spike suppression TSP
(SDA and SCL pins)
â
250 20 +0.1 250
ns (Note 1), CB ⤠100 pF
CB
â
50
â
50
ns (Notes 1, 3)
Write cycle time
TWC
â
10
â
10
ms Byte or Page mode
Endurance
1M
â
1M
â cycles 25°C, VCC = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undeï¬ned region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS speciï¬cations are due to Schmitt trigger inputs which provide improved noise
spike suppression. This eliminates the need for a TI speciï¬cation for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciï¬c
application, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-1: BUS TIMING DATA
TF
SCL
TSU:STA
SDA
IN
TSP
TLOW
THD:STA
THIGH
THD:DAT
SDA
OUT
TAA
THD:STA
TAA
TR
TSU:DAT
TSU:STO
TBUF
© 1997 Microchip Technology Inc.
DS21224A-page 3
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