MCP40D17 Datasheet, PDF (47/66 Pages) Microchip Technology – 7-Bit Single I2C™ (with Command Code) Digital POT with Volatile Memory in SC70

7.0 DESIGN CONSIDERATIONS
In the design of a system with the MCP40D17/18/19
devices, the following considerations should be taken
into account. These are:
• The Power Supply
• The Layout
In the design of a system with the MCP40D17/18/19
devices, the following considerations should be taken
into account:
• Power Supply Considerations
• Layout Considerations
7.1 Power Supply Considerations
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 7-1 illustrates an
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close to the device power pin (V_DD) as possible (within
4 mm).
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, V_DD and
V_SS should reside on the analog plane.
V_DD
0.1 µF
V_DD
0.1 µF
MCP40D17/18/19
7.2 Layout Considerations
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP40D17/18/19’s
performance. Careful board layout will minimize these
effects and increase the Signal-to-Noise Ratio (SNR).
Bench testing has shown that a multi-layer board
utilizing a low-inductance ground plane, isolated inputs,
isolated outputs and proper decoupling are critical to
achieving the performance that the silicon is capable of
providing. Particularly harsh environments may require
shielding of critical signals.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
7.2.1 RESISTOR TEMPCO
Characterization curves of the resistor temperature
coefficient (Tempco) are shown in Figure 2-11,
Figure 2-29, Figure 2-47, and Figure 2-65.
These curves show that the resistor network is
designed to correct for the change in resistance as
temperature increases. This technique reduces the
end to end change is R_AB resistance.
A
SCL
W
B
SDA
FIGURE 7-1:
Connections.
V_SS
V_SS
Typical Microcontroller
© 2009 Microchip Technology Inc.
DS22152B-page 47