MCP3901_10 Datasheet, PDF (47/60 Pages) Microchip Technology – Two-Channel Analog Front End

MCP3901
REGISTER 7-5: STATUS AND COMMUNICATION REGISTER: ADDRESS 0x09
R/W-1 R/W-0
READ<1> READ<0>
bit 7
R/W-1
DR_LTY
R/W-0
DR_HIZN
R/W-0
DRMODE<1>
R/W-0
R-1
DRMODE<0> DRSTATUS_CH1
R-1
DRSTATUS_CH0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5
bit 4
bit 3-2
bit 1-0
READ<1:0>: Address Loop Setting bits
11 = Address counter loops on entire register map
10 = Address counter loops on register types (default)
01 = Address counter loops on register groups
00 = Address not incremented, continually read same single register
DR_LTY: Data Ready Latency Control bit
1 = “No Latency” Conversion, DR pulses after 3 DRCLK periods (default)
0 = Unsettled Data is available after every DRCLK period
DR_HIZN: Data Ready Pin Inactive State Control bit
1 = The data ready pin default state is a logic high when data is NOT ready
0 = The data ready pin default state is high-impedance when data is NOT ready (default)
DRMODE<1:0>: Data Ready Pin (DR) Control bits
11 = Both Data Ready pulses from ADC0 and ADC Channel 1 are output on the DR pin.
10 = Data Ready pulses from ADC Channel 1 are output on the DR pin. DR from ADC Channel 0 are not
present on the pin.
01 = Data Ready pulses from ADC Channel 0 are output on the DR pin. DR from ADC Channel 1 are not
present on the pin.
00 = Data Ready pulses from the lagging ADC between the two are output on the DR pin. The lagging
ADC selection depends on the PHASE register and on the OSR (default).
DRSTATUS_CH<1:0>: Data Ready Status bits
11 = ADC Channel 1 and Channel 0 data is not ready (default)
10 = ADC Channel 1 data is not ready, ADC Channel 0 data is ready
01 = ADC Channel 0 data is not ready, ADC Channel 1 data is ready
00 = ADC Channel 1 and Channel 0 data is ready
© 2010 Microchip Technology Inc.
DS22192C-page 47