MCP3901_10 Datasheet, PDF (20/60 Pages) Microchip Technology – Two-Channel Analog Front End

MCP3901
Since this is the output data rate, and since the
decimation filter is a SINC (or notch) filter, there is a
notch in the filter transfer function at each integer
multiple of this rate.
The following table describes the various combinations
of OSR and PRESCALE, and their associated AMCLK,
DMCLK and DRCLK rates.
TABLE 4-2: DEVICE DATA RATES IN FUNCTION OF MCLK, OSR AND PRESCALE
PRE
<1:0>
OSR <1:0> OSR
AMCLK
DMCLK
DRCLK
DRCLK
(ksps)
SINAD
(dB)
ENOB
(bits)
1 1 1 1 256 MCLK/8 MCLK/32 MCLK/8192 0.4882
1
1
1 0 128
MCLK/8
MCLK/32 MCLK/4096
0.976
1 1 0 1 64
MCLK/8 MCLK/32 MCLK/2048
1.95
1 1 0 0 32
MCLK/8 MCLK/32 MCLK/1024
3.9
1
0
1 1 256
MCLK/4
MCLK/16 MCLK/4096
0.976
1 0 1 0 128 MCLK/4 MCLK/16 MCLK/2048
1.95
1 0 0 1 64
MCLK/4 MCLK/16 MCLK/1024
3.9
1 0 0 0 32
MCLK/4 MCLK/16 MCLK/512
7.8125
0
1
1 1 256
MCLK/2
MCLK/8 MCLK/2048
1.95
0
1
1 0 128
MCLK/2
MCLK/8 MCLK/1024
3.9
0 1 0 1 64
MCLK/2
MCLK/8 MCLK/512
7.8125
0 1 0 0 32
MCLK/2
MCLK/8 MCLK/256
15.625
0 0 1 1 256
MCLK
MCLK/4 MCLK/1024
3.9
0 0 1 0 128
MCLK
MCLK/4 MCLK/512
7.8125
0 0 0 1 64
MCLK
MCLK/4 MCLK/256
15.625
0 0 0 0 32
MCLK
MCLK/4 MCLK/128
31.25
Note: For OSR = 32 and 64, DITHER = 0. For OSR = 128 and 256, DITHER = 1.
91.4
14.89
86.6
14.10
78.7
12.78
68.2
11.04
91.4
14.89
86.6
14.10
78.7
12.78
68.2
11.04
91.4
14.89
86.6
14.10
78.7
12.78
68.2
11.04
91.4
14.89
86.6
14.10
78.7
12.78
68.2
11.04
4.5 Oversampling Ratio (OSR)
The ratio of the sampling frequency to the output data
rate is OSR = DMCLK/DRCLK. The default OSR is 64
or with MCLK = 4 MHz and PRESCALE = 1,
AMCLK = 4 MHz, f_S = 1 MHz, f_D = 15.625 ksps. The
following bits in the CONFIG1 register are used to
change the Oversampling Ratio (OSR).
TABLE 4-3:
CONFIG
OSR<1:0>
0
0
0
1
1
0
1
1
MCP3901 OVERSAMPLING
RATIO SETTINGS
OVERSAMPLING RATIO
OSR
32
64 (default)
128
256
4.6 Offset Error
This is the error induced by the ADC when the inputs
are shorted together (V_IN = 0V). The specification
incorporates both PGA and ADC offset contributions.
This error varies with PGA and OSR settings. The
offset is different on each channel and varies from chip
to chip. This offset error can easily be calibrated out by
a MCU with a subtraction. The offset is specified in mV.
The offset on the MCP3901 has a low temperature
coefficient; see Section 2.0 “Typical Performance
Curves”.
4.7 Gain Error
This is the error induced by the ADC on the slope of the
transfer function. It is the deviation expressed in percent
(%) compared to the ideal transfer function defined by
Equation 5-3. The specification incorporates both PGA
and ADC gain error contributions, but not the V_REF
contribution (it is measured with an external V_REF). This
error varies with PGA and OSR settings.
The gain error on the MCP3901 has a low temperature
coefficient; see the typical performance curves for
more information, Figure 2-24 and Figure 2-25.
DS22192C-page 20
© 2010 Microchip Technology Inc.