MCP3901_10 Datasheet, PDF (31/60 Pages) Microchip Technology – Two-Channel Analog Front End

5.10.1 PHASE DELAY LIMITS
The phase delay can only go from -OSR/2 to
+OSR/2 – 1. This sets the fine phase resolution. The
PHASE register is coded with 2’s complement.
If larger delays between the two channels are needed,
they can be implemented externally to the chip with an
MCU. A FIFO in the MCU can save incoming data from
the leading channel for a number N of DRCLK clocks.
In this case, DRCLK would represent the coarse timing
resolution, and DMCLK, the fine timing resolution. The
total delay will then be equal to:
Delay = N/DRCLK + PHASE/DMCLK
The Phase Delay register can be programmed once
with the OSR = 256 setting and will adjust to the OSR
automatically afterwards, without the need to change
the value of the PHASE register.
• OSR = 256: The delay can go from -128 to +127.
PHASE<7> is the sign bit, PHASE<6> is the MSB
and PHASE<0> is the LSB.
• OSR = 128: The delay can go from -64 to +63.
PHASE<6> is the sign bit, PHASE<5> is the MSB
and PHASE<0> is the LSB.
• OSR = 64: The delay can go from -32 to +31.
PHASE<5> is the sign bit, PHASE<4> is the MSB
and PHASE<0> is the LSB.
• OSR = 32: The delay can go from -16 to +15.
PHASE<4> is the sign bit, PHASE<3> is the MSB
and PHASE<0> is the LSB.
TABLE 5-8: PHASE VALUES WITH
MCLK = 4 MHZ, OSR = 256
PHASE
Hex
Register Value
Delay
(CH0 relative
to CH1)
01111111
01111110
00000001
00000000
11111111
10000001
10000000
0x7F
0x7E
0x01
0x00
0xFF
0x81
0x80
+127 µs
+126 µs
+1 µs
0 µs
-1 µs
-127 µs
-128 µs
MCP3901
5.11 Crystal Oscillator
The MCP3901 includes a Pierce type crystal oscillator
with very high stability and ensures very low tempera-
ture and jitter for the clock generation. This oscillator
can handle up to 16.384 MHz crystal frequencies pro-
vided that proper load capacitances and the quartz
quality factor are used.
For keeping specified ADC accuracy, AMCLK should
be kept between 1 and 5 MHz with BOOST off or 1 and
8.192 MHz with BOOST on. Larger MCLK frequencies
can be used provided the prescaler clock settings allow
the AMCLK to respect these ranges.
For a proper start-up, the load capacitors of the crystal
should be connected between OSC1 and DGND, and
between OSC2 and DGND. They should also respect
the following equation:
EQUATION 5-6:
Where:
R_M
<
1.6
×
10⁶
×
⎛
⎝
C-----_L^---_O^f---_A^----_D^{- ⎠⎞}
2
f = Crystal frequency in MHz
C_LOAD = Load capacitance in pF including
parasitics from the PCB
R_M = Motional resistance in ohms of
the quartz
When CLKEXT = 1, the crystal oscillator is bypassed
by a digital buffer to allow direct clock input for an
external clock (see Figure 1-5).
© 2010 Microchip Technology Inc.
DS22192C-page 31