41228F Datasheet, PDF (4/22 Pages) –

PIC10F200/202/204/206
3.0 PROGRAM/VERIFY MODE
In Program/Verify mode, the program memory and the
configuration memory can be accessed and
programmed in serial fashion. ICSPDAT and ICSPCLK
are used for the data and the clock, respectively. All
commands and data words are transmitted LSb first.
Data changes on the rising edge of the ICSPCLK and
is latched on the falling edge. In Program/Verify mode,
both the ICSPDAT and ICSPCLK are Schmitt Trigger
inputs. The sequence that enters the device into
Program/Verify mode places all other logic into the
Reset state. Upon entering Program/Verify mode, all
I/Os are automatically configured as high-impedance
inputs and the address is cleared.
3.1 High-Voltage Program/Verify mode
Entry and Exit
There are two different methods of entering Program/
Verify mode via high-voltage:
• VDD- First Entry mode
• VPP- First Entry mode
3.1.1 VPP- FIRST ENTRY MODE
To enter Program/Verify mode via the VPP- first
method, please follow the sequence below:
1. Hold ICSPCLK and ICSPDAT low. All other pins
should be un-powered.
2. Raise the voltage on MCLR/VPP from 0V to
VIHH.
3. Raise the voltage on VDD from 0V to the desired
operating voltage.
The VPP- first entry prevents the device from executing
code prior to entering Program/Verify mode. For
example, when Configuration Word 1 has MCLR
disabled (MCLRE = 0), the power-up time is disabled
(PWRTE = 0), the internal oscillator is selected
(FOSC = 100), and ICSPCLK and ICSPDAT pins are
driven by the user application, the device will execute
code. Since this may prevent entry, VPP- First Entry
mode is strongly recommended. See the timing
diagram in Figure 3-1.
FIGURE 3-1:
PROGRAMMING MODE
ENTRY – VPP FIRST
TPPDP THLD0
VIHH
VPP
VIL
VDD
ICSPDAT
ICSPCLK
3.1.2 VDD- FIRST ENTRY MODE
To enter Program/verify mode via the VDD- first
method, please follow the sequence below:
1. Hold ICSPCLK and ICSPDAT low.
2. Raise the voltage on VDD from 0V to the desired
operating voltage (VIL to VDD).
3. Raise the voltage on MCLR/VPP from VDD or
below, to VIHH.
The VDD- first method is useful when programming the
device when VDD is already applied, for it is not
necessary to disconnect VDD to enter Program/Verify
mode. See the timing diagram in Figure 3-2.
FIGURE 3-2:
PROGRAMMING MODE
ENTRY – VDD FIRST
TPPDP THLD0
VIHH
VPP
VIL
VDD
ICSPDAT
ICSPCLK
DS41228F-page 4
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