DSPIC33FJ64MC204-I Datasheet, PDF (392/460 Pages) Microchip Technology – 16-bit Digital Signal Controllers (up to 128 KB Flash and 16K SRAM) with Motor Control PWM and Advanced Analog

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
TABLE 31-38: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING
REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Param
No.
Symbol
Characteristic⁽¹⁾
Min
Typ⁽²⁾ Max Units
Conditions
SP70 TscP
Maximum SCK Input Frequency
—
—
15 MHz See Note 3
SP72 TscF
SCKx Input Fall Time
—
—
—
ns See parameter DO32
and Note 4
SP73 TscR
SCKx Input Rise Time
—
—
—
ns See parameter DO31
and Note 4
SP30 TdoF
SDOx Data Output Fall Time
—
—
—
ns See parameter DO32
and Note 4
SP31 TdoR
SDOx Data Output Rise Time
SP35 TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
—
ns See parameter DO31
and Note 4
—
6
20 ns
—
SP36 TdoV2scH, SDOx Data Output Setup to
30
—
—
ns
—
TdoV2scL First SCKx Edge
SP40 TdiV2scH, Setup Time of SDIx Data Input
30
—
—
ns
—
TdiV2scL to SCKx Edge
SP41 TscH2diL, Hold Time of SDIx Data Input
30
—
—
ns
—
TscL2diL to SCKx Edge
SP50 TssL2scH, SSx ↓to SCKx ↑ or SCKx Input
120
—
—
ns
—
TssL2scL
SP51 TssH2doZ SSx ↑ to SDOx Output
High-Impedance⁽⁴⁾
10
—
50
ns
—
SP52 TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40 —
—
ns ^{See Note 4}
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must
not violate this specification.
4: Assumes 50 pF load on all SPIx pins.
DS70291G-page 392
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