PIC18F2X1X_07 Datasheet, PDF (372/378 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2X1X/4X1X
Serial Data Out ........................................................ 151
Slave Mode .............................................................. 157
Slave Select ............................................................. 151
Slave Select Synchronization .................................. 157
SPI Clock ................................................................. 156
Typical Connection .................................................. 155
SS .................................................................................... 151
SSPOV ............................................................................. 181
SSPOV Status Flag .......................................................... 181
SSPSTAT Register
R/W Bit ............................................................. 164, 165
Stack Full/Underflow Resets .............................................. 56
SUBFSR ........................................................................... 303
SUBFWB .......................................................................... 292
SUBLW ............................................................................ 293
SUBULNK ........................................................................ 303
SUBWF ............................................................................ 293
SUBWFB .......................................................................... 294
SWAPF ............................................................................ 294
T
Table Pointer Operations (table) ........................................ 76
Table Reads/Table Writes .................................................. 56
TBLRD ............................................................................. 295
TBLWT ............................................................................. 296
Time-out in Various Situations (table) ................................ 45
Timer0 .............................................................................. 113
16-Bit Mode Timer Reads and Writes ...................... 114
Associated Registers ............................................... 115
Clock Source Edge Select (T0SE Bit) ...................... 114
Clock Source Select (T0CS Bit) ............................... 114
Operation ................................................................. 114
Overflow Interrupt .................................................... 115
Prescaler .................................................................. 115
Prescaler. See Prescaler, Timer0.
Timer1 .............................................................................. 117
16-Bit Read/Write Mode ........................................... 119
Associated Registers ............................................... 121
Interrupt .................................................................... 120
Operation ................................................................. 118
Oscillator .......................................................... 117, 119
Oscillator Layout Considerations ............................. 120
Overflow Interrupt .................................................... 117
Resetting, Using the CCP
Special Event Trigger ....................................... 120
Special Event Trigger (ECCP) ................................. 138
TMR1H Register ...................................................... 117
TMR1L Register ....................................................... 117
Use as a Real-Time Clock ....................................... 120
Timer2 .............................................................................. 123
Associated Registers ............................................... 124
Interrupt .................................................................... 124
Operation ................................................................. 123
Output ...................................................................... 124
PR2 Register .................................................... 134, 139
TMR2 to PR2 Match Interrupt .......................... 134, 139
Timer3 .............................................................................. 125
16-Bit Read/Write Mode ........................................... 127
Associated Registers ............................................... 127
Operation ................................................................. 126
Oscillator .......................................................... 125, 127
Overflow Interrupt ............................................ 125, 127
Special Event Trigger (CCP) .................................... 127
TMR3H Register ...................................................... 125
TMR3L Register ....................................................... 125
Timing Diagrams
A/D Conversion ........................................................ 348
Acknowledge Sequence .......................................... 184
Asynchronous Reception ......................................... 203
Asynchronous Transmission .................................... 201
Asynchronous Transmission (Back to Back) ........... 201
Automatic Baud Rate Calculation ............................ 199
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 204
Auto-Wake-up Bit (WUE) During Sleep ................... 204
Baud Rate Generator with Clock Arbitration ............ 178
BRG Overflow Sequence ......................................... 199
BRG Reset Due to SDA Arbitration
During Start Condition ..................................... 187
Brown-out Reset (BOR) ........................................... 334
Bus Collision During a Repeated Start
Condition (Case 1) ........................................... 188
Bus Collision During a Repeated Start
Condition (Case 2) ........................................... 188
Bus Collision During a Start
Condition (SCL = 0) ......................................... 187
Bus Collision During a Start
Condition (SDA only) ....................................... 186
Bus Collision During a Stop
Condition (Case 1) ........................................... 189
Bus Collision During a Stop
Condition (Case 2) ........................................... 189
Bus Collision for Transmit and Acknowledge .......... 185
Capture/Compare/PWM (CCP) ............................... 336
CLKO and I/O .......................................................... 333
Clock Synchronization ............................................. 171
Clock/Instruction Cycle .............................................. 57
Example SPI Master Mode (CKE = 0) ..................... 338
Example SPI Master Mode (CKE = 1) ..................... 339
Example SPI Slave Mode (CKE = 0) ....................... 340
Example SPI Slave Mode (CKE = 1) ....................... 341
External Clock (All Modes except PLL) ................... 331
Fail-Safe Clock Monitor ........................................... 250
First Start Bit Timing ................................................ 179
Full-Bridge PWM Output .......................................... 143
Half-Bridge PWM Output ......................................... 142
High/Low-Voltage Detect Characteristics ................ 328
High-Voltage Detect (VDIRMAG = 1) ...................... 234
I²C Bus Data ............................................................ 342
I²C Bus Start/Stop Bits ............................................ 342
I²C Master Mode (7 or 10-Bit Transmission) ........... 182
I²C Master Mode (7-Bit Reception) .......................... 183
I²C Slave Mode (10-Bit Reception, SEN = 0) .......... 168
I²C Slave Mode (10-Bit Reception, SEN = 1) .......... 173
I²C Slave Mode (10-Bit Transmission) .................... 169
I²C Slave Mode (7-Bit Reception, SEN = 0) ............ 166
I²C Slave Mode (7-Bit Reception, SEN = 1) ............ 172
I²C Slave Mode (7-Bit Transmission) ...................... 167
I²C Slave Mode General Call Address
Sequence (7 or 10-Bit Address Mode) ............ 174
I²C Stop Condition Receive or
Transmit Mode ................................................. 184
Low-Voltage Detect (VDIRMAG = 0) ....................... 233
Master SSP I²C Bus Data ........................................ 344
Master SSP I²C Bus Start/Stop Bits ........................ 344
Parallel Slave Port
(PIC18F4410/4510/4515/4610) ....................... 337
Parallel Slave Port (PSP) Read ............................... 111
Parallel Slave Port (PSP) Write ............................... 111
DS39636C-page 370
Preliminary
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