PIC18F1220 Datasheet, PDF (305/310 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology

Timing Diagrams
A/D Conversion ........................................................ 267
Asynchronous Reception ......................................... 144
Asynchronous Transmission .................................... 141
Asynchronous Transmission
(Back to Back) .................................................. 142
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................. 145
Auto-Wake-up Bit (WUE) During Sleep ................... 145
Brown-out Reset (BOR) ........................................... 262
Capture/Compare/PWM (All CCP Modules) ............ 264
CLKO and I/O .......................................................... 261
Clock/Instruction Cycle .............................................. 45
EUSART Synchronous Receive
(Master/Slave) .................................................. 266
EUSART SynchronousTransmission
(Master/Slave) .................................................. 265
External Clock (All Modes Except PLL) ................... 259
Fail-Safe Clock Monitor ............................................ 183
Low-Voltage Detect .................................................. 168
Low-Voltage Detect Characteristics ......................... 255
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) ..................................... 128
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) ..................................... 128
Reset, Watchdog Timer (WDT),
Oscillator Start-up Timer (OST) and
Power-up Timer (PWRT) ................................. 262
Send Break Character Sequence ............................ 147
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 40
Synchronous Reception
(Master Mode, SREN) ...................................... 150
Synchronous Transmission ...................................... 148
Synchronous Transmission
(Through TXEN) ............................................... 149
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD) ........................................... 40
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 1 ....................... 39
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 2 ....................... 39
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise TPWRT) .............. 39
Timer0 and Timer1 External Clock .......................... 263
Transition for Entry to SEC_IDLE Mode .................... 24
Transition for Entry to SEC_RUN Mode .................... 26
Transition for Entry to Sleep Mode ............................ 22
PIC18F1220/1320
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ........................................ 181
Transition for Wake from PRI_IDLE Mode ................ 23
Transition for Wake from RC_RUN Mode
(RC_RUN to PRI_RUN) .................................... 25
Transition for Wake from SEC_RUN Mode
(HSPLL) ............................................................. 24
Transition for Wake from Sleep (HSPLL) .................. 22
Transition to PRI_IDLE Mode .................................... 23
Transition to RC_IDLE Mode ..................................... 25
Transition to RC_RUN Mode ..................................... 27
Timing Diagrams and Specifications ............................... 259
Capture/Compare/PWM Requirements
(All CCP Modules) ........................................... 265
CLKO and I/O Requirements ................................... 261
EUSART Synchronous Receive
Requirements .................................................. 266
EUSART Synchronous Transmission
Requirements .................................................. 265
External Clock Requirements .................................. 259
Internal RC Accuracy ............................................... 260
PLL Clock, HS/HSPLL Mode
(VDD = 4.2V to 5.5V) ........................................ 260
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and
Brown-out Reset Requirements ...................... 263
Timer0 and Timer1 External Clock
Requirements .................................................. 264
Top-of-Stack Access .......................................................... 42
TSTFSZ ........................................................................... 231
Two-Speed Start-up ..................................................171, 181
Two-Word Instructions ....................................................... 46
Example Cases .......................................................... 46
TXSTA Register
BRGH Bit ................................................................. 135
W
Watchdog Timer (WDT) ............................................171, 180
Associated Registers ............................................... 181
Control Register ....................................................... 180
During Oscillator Failure .......................................... 182
Programming Considerations .................................. 180
WWW, On-Line Support ...................................................... 4
X
XORLW ............................................................................ 231
XORWF ........................................................................... 232
 2004 Microchip Technology Inc.
DS39605C-page 303