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PIC18F1220 Datasheet, PDF (202/310 Pages) Microchip Technology – 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology | |||
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PIC18F1220/1320
BCF
Bit Clear f
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
[ label ] BCF
0 ⤠f ⤠255
0â¤bâ¤7
a â [0,1]
0 â f<b>
None
f,b[,a]
1001 bbba ffff ffff
Bit âbâ in register âfâ is cleared. If âaâ
is â0â, the Access Bank will be
selected, overriding the BSR value.
If âaâ = 1, then the bank will be
selected as per the BSR value
(default).
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register âfâ
Q3
Process
Data
Q4
Write
register âfâ
Example:
BCF
Before Instruction
FLAG_REG =
After Instruction
FLAG_REG =
FLAG_REG, 7
0xC7
0x47
BN
Branch if Negative
Syntax:
[ label ] BN n
Operands:
-128 ⤠n ⤠127
Operation:
if Negative bit is â1â
(PC) + 2 + 2n â PC
Status Affected: None
Encoding:
1110 0110 nnnn nnnn
Description:
If the Negative bit is â1â, then the
program will branch.
The 2âs complement number â2nâ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then
a two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
No
operation
If No Jump:
Read literal
ânâ
No
operation
Process
Data
No
operation
Write to PC
No
operation
Q1
Q2
Q3
Q4
Decode
Read literal
ânâ
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Negative =
PC
=
If Negative =
PC
=
BN Jump
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
DS39605C-page 200
 2004 Microchip Technology Inc.
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