DSPIC33FJ32MC202 Datasheet, PDF (288/292 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
PLLFBD (PLL Feedback Divisor) .............................. 101
PTCON (PWM Time Base Control) .......................... 157
PTMR (PWM Timer Count Value)............................. 158
PTPER (PWM Time Base Period) ............................ 158
PWMxCON1 (PWM Control 1).................................. 160
PWMxCON2 (PWM Control 2).................................. 161
PxDTCON1 (Dead-Time Control 1) .......................... 162
PxDTCON2 (Dead-Time Control 2) .......................... 163
PxFLTACON (Fault A Control).................................. 164
PxOVDCON (Override Control) ................................ 165
PxSECMP (Special Event Compare) ........................ 159
QEICON (QEI Control).............................................. 173
RCON (Reset Control) ................................................ 58
SPIxCON1 (SPIx Control 1) ...................................... 182
SPIxCON2 (SPIx Control 2) ...................................... 184
SPIxSTAT (SPIx Status and Control) ....................... 181
SR (CPU Status) ................................................... 16, 68
T1CON (Timer1 Control)........................................... 134
T2CON Control) ........................................................ 138
T3CON Control ......................................................... 139
UxMODE (UARTx Mode) .......................................... 198
UxSTA (UARTx Status and Control) ......................... 200
Reset
Clock Source Selection ............................................... 60
Special Function Register Reset States ..................... 61
Times .......................................................................... 60
Reset Sequence.................................................................. 63
Resets ................................................................................. 57
S
Serial Peripheral Interface (SPI) ....................................... 177
Setup for Continuous Output Pulse Generation................ 143
Setup for Single Output Pulse Generation ........................ 143
Software Simulator (MPLAB SIM)..................................... 234
Software Stack Pointer, Frame Pointer
CALLL Stack Frame.................................................... 42
Special Features of the CPU............................................. 217
SPI
Master, Frame Master Connection ........................... 179
Master/Slave Connection .......................................... 179
Slave, Frame Master Connection ............................. 180
Slave, Frame Slave Connection ............................... 180
SPI Module
SPI1 Register Map ...................................................... 35
Symbols Used in Opcode Descriptions............................. 226
System Control
Register Map............................................................... 40
T
Temperature and Voltage Specifications
AC ............................................................................. 246
Timer1 ............................................................................... 133
Timer2/3 ............................................................................ 135
Timing Characteristics
CLKO and I/O ........................................................... 249
Timing Diagrams
10-bit ADC Conversion (CHPS = 01, SIMSAM = 0,
ASAM = 0, SSRC = 000) .................................. 273
10-bit ADC Conversion (CHPS = 01,
SIMSAM = 0, ASAM = 1, SSRC = 111,
SAMC = 00001) ................................................ 273
12-bit ADC Conversion (ASAM = 0, SSRC = 000) ... 272
Center-Aligned PWM ................................................ 152
Dead-Time ................................................................ 153
Edge-Aligned PWM................................................... 152
External Clock ........................................................... 247
I2Cx Bus Data (Master Mode) .................................. 265
I2Cx Bus Data (Slave Mode) .................................... 267
I2Cx Bus Start/Stop Bits (Master Mode)................... 265
I2Cx Bus Start/Stop Bits (Slave Mode)..................... 267
Input Capture (CAPx) ............................................... 255
Motor Control PWM .................................................. 257
Motor Control PWM Fault ......................................... 257
OC/PWM................................................................... 256
Output Compare (OCx)............................................. 255
QEA/QEB Input ........................................................ 258
QEI Module Index Pulse ........................................... 259
Reset, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer............................... 250
SPIx Master Mode (CKE = 0) ................................... 260
SPIx Master Mode (CKE = 1) ................................... 261
SPIx Slave Mode (CKE = 0) ..................................... 262
SPIx Slave Mode (CKE = 1) ..................................... 263
Timer1, 2, 3 External Clock ...................................... 252
TimerQ (QEI Module) External Clock ....................... 254
Timing Requirements
CLKO and I/O ........................................................... 249
External Clock........................................................... 247
Input Capture ............................................................ 255
Timing Specifications
10-bit ADC Conversion Requirements...................... 274
12-bit ADC Conversion Requirements...................... 272
I2Cx Bus Data Requirements (Master Mode)........... 266
I2Cx Bus Data Requirements (Slave Mode)............. 268
Motor Control PWM Requirements........................... 257
Output Compare Requirements................................ 255
PLL Clock ................................................................. 248
QEI External Clock Requirements ............................ 254
QEI Index Pulse Requirements ................................ 259
Quadrature Decoder Requirements.......................... 258
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset
Requirements ................................................... 251
Simple OC/PWM Mode Requirements ..................... 256
SPIx Master Mode (CKE = 0) Requirements............ 260
SPIx Master Mode (CKE = 1) Requirements............ 261
SPIx Slave Mode (CKE = 0) Requirements.............. 262
SPIx Slave Mode (CKE = 1) Requirements.............. 264
Timer1 External Clock Requirements ....................... 252
Timer2 External Clock Requirements ....................... 253
Timer3 External Clock Requirements ....................... 253
U
UART
Baud Rate
Generator (BRG) .............................................. 196
Break and Sync Transmit Sequence ........................ 197
Flow Control Using UxCTS and UxRTS Pins ........... 197
Receiving in 8-bit or 9-bit Data Mode ....................... 197
Transmitting in 8-bit Data Mode................................ 197
Transmitting in 9-bit Data Mode................................ 197
UART Module
UART1 Register Map.................................................. 35
Universal Asynchronous Receiver Transmitter (UART) ... 195
V
Voltage Regulator (On-Chip) ............................................ 221
W
Watchdog Timer (WDT)............................................ 217, 222
Programming Considerations ................................... 222
WWW Address ................................................................. 287
WWW, On-Line Support ....................................................... 7
DS70283B-page 286
Preliminary
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