DSPIC33FJ32MC202 Datasheet, PDF (197/292 Pages) Microchip Technology – High-Performance, 16-bit Microcontrollers

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
18.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
Note:
This data sheet summarizes the features
of the dsPIC33FJ32MC202/204 and
dsPIC33FJ16MC304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC33F
Family Reference Manual”. Please see
the Microchip web site (www.micro-
chip.com) for the latest dsPIC33F Family
Reference Manual sections.
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules avail-
able in the dsPIC33FJ32MC202/204 and
dsPIC33FJ16MC304 device family. The UART is a full-
duplex asynchronous system that can communicate
with peripheral devices, such as personal computers,
LIN, RS-232 and RS-485 interfaces. The module also
supports a hardware flow control option with the
UxCTS and UxRTS pins and also includes an IrDA^®
encoder and decoder.
The primary features of the UART module are:
• Full-Duplex, 8- or 9-bit Data Transmission through
the UxTX and UxRX pins
• Even, Odd or No Parity Options (for 8-bit data)
• One or two stop bits
• Hardware flow control option with UxCTS and
UxRTS pins
• Fully integrated Baud Rate Generator with 16-bit
prescaler
• Baud rates ranging from 1 Mbps to 15 Mbps at
16 MIPS
• 4-deep First-In First-Out (FIFO) Transmit Data
buffer
• 4-deep FIFO Receive Data buffer
• Parity, framing and buffer overrun error detection
• Support for 9-bit mode with Address Detect
(9th bit = 1)
• Transmit and Receive interrupts
• A separate interrupt for all UART error conditions
• Loopback mode for diagnostic support
• Support for sync and break characters
• Support for automatic baud rate detection
• IrDA encoder and decoder logic
• 16x baud clock output for IrDA support
A simplified block diagram of the UART module is
shown in Figure 18-1. The UART module consists of
these key hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
FIGURE 18-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA^®
BCLK
Hardware Flow Control
UART Receiver
UxRTS
UxCTS
UxRX
UART Transmitter
UxTX
© 2007 Microchip Technology Inc.
Preliminary
DS70283B-page 195