DSPIC33FJ16GP101_13 Datasheet, PDF (288/386 Pages) Microchip Technology – 16-Bit Digital Signal Controllers up to 32-Kbyte Flash and 2-Kbyte SRAM

dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Param
No.
Symbol
Characteristic
Min
Typ⁽¹⁾
Max Units
Conditions
VIL
Input Low Voltage
DI10
I/O Pins
VSS
— 0.2 VDD V
DI15
MCLR
VSS
— 0.2 VDD V
DI18
I/O Pins with SDAx, SCLx
VSS
— 0.3 VDD V SMBus disabled
DI19
I/O Pins with SDAx, SCLx
VSS
—
0.8
V SMBus enabled
VIH
DI20
Input High Voltage
I/O Pins Not 5V Tolerant⁽⁴⁾
I/O Pins 5V Tolerant⁽⁴⁾
0.7 VDD
—
VDD
V
0.7 VDD
—
5.5
V
DI28
SDAx, SCLx
0.7 VDD
—
5.5
V SMBus disabled
DI29
SDAx, SCLx
2.1
—
5.5
V SMBus enabled
ICNPU CNx Pull-up Current
DI30
50
250
450
A VDD = 3.3V, VPIN = VSS
IIL
Input Leakage Current^(2,3)
DI50
I/O Pins 5V Tolerant⁽⁴⁾
—
—
±2
A VSS  VPIN  VDD,
Pin at high-impedance
DI51
I/O Pins Not 5V Tolerant⁽⁴⁾
—
—
±1
A VSS  VPIN  VDD,
Pin at high-impedance,
-40°C  TA  +85°C
DI51a
I/O Pins Not 5V Tolerant⁽⁴⁾
—
—
±2
A Shared with external
reference pins,
-40°C  TA  +85°C
DI51b
I/O Pins Not 5V Tolerant⁽⁴⁾
—
—
±3.5
A VSS  VPIN  VDD,
Pin at high-impedance,
-40°C  TA  +125°C
DI51c
I/O Pins Not 5V Tolerant⁽⁴⁾
—
—
±8
A Analog pins shared with
external
reference pins,
-40°C  TA  +125°C
DI55
MCLR
—
—
±2
A VSS VPIN VDD
DI56
OSC1
—
—
±2
A VSS VPIN VDD,
XT and HS modes
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current can be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
4: See “Pin Diagrams” for the 5V tolerant I/O pins.
5: VIL source < (VSS – 0.3). Characterized but not tested.
6: Non-5V tolerant pins, VIH source > (VDD + 0.3), 5V tolerant pins, VIH source > 5.5V. Characterized but not
tested.
7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins, not excluded under IICL or IICH conditions, are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
DS70652E-page 288
 2011-2012 Microchip Technology Inc.