EVB-LAN9252 Datasheet, PDF (26/55 Pages) Microchip Technology – EVB-LAN9252-HBI-SPI-SQI-GPIO EtherCAT® HBI/SPI+GPIO

EVB-LAN9252-HBI-SPI-SQI-GPIO EtherCAT® HBI/SPI+GPIO User’s Guide
TABLE 2-22: DIG-IO MODE P1 & P2 HEADER SIGNALS (CONTINUED)
HBI Indexed
HBI Multiplexed
DIG-IO
P1/P2 Pin
D10
AD10
DIGIO4
P1.14
D9
AD9
LATCH_IN
P1.13
D8
AD8
DIGIO2
P1.19
D7
AD7
DIGIO1
P1.4
D6
AD6
DIGIO0
P1.3
D5
AD5
OUTVALID
P1.22
D4
AD4
DIGIO3
P1.23
D3
AD3
WD_TRIG
P1.6
D2
AD2
SOF
P1.5
D1
AD1
EOF
P1.24
D0
AD0
WD_STATE
P1.25
2.5.2 SPI+GPIO on P1 and P2 Headers (up to 16 bits supported)
The LAN9252 supports an SPI+16GPIO mode, where these signals can be probed on
the P1 and P2 headers. To enable SPI+16GPIO mode, from the default state of the
board, the SW26 switch must be changed to the PIM position (upward) and SW19,
SW20, and SW21 must be changed to the downward side. The respective
SPI+16GPIO signal mappings on the P1 and P2 headers are detailed in Table 2-23.
Note 1: In the default state, headers P1 and P2 are not assembled. These headers
can each be populated with a Molex 87758-4616.
2: The user must ensure the respective mode’s demo code is programmed
into EEPROM.
TABLE 2-23: SPI+16GPIO MODE P1 & P2 HEADER SIGNALS
HBI Indexed
HBI Multiplexed
SPI+16GPIO
RD/RD_WR
RD/RD_WR
GPI15/GPO15
WR/ENB
WR/ENB
GPI14/GPO14
CS
CS
GPI13/GPO13
A4
-
GPI12/GPO12
A3
-
GPI11/GPO11
A2
ALEHI
GPI10/GPO10
A0/D15
AD15
GPI9/GPO9
D14
AD14
GPI8/GPO8
D13
AD13
GPI7/GPO7
D12
AD12
GPI6/GPO6
D11
AD11
GPI5/GPO5
D10
AD10
GPI4/GPO4
D9
AD9
SCK
D8
AD8
GPI2/GPO2
D7
AD7
GPI1/GPO1
D6
AD6
GPI0/GPO0
D5
AD5
SCS#
D4
AD4
GPI3/GPO3
D3
AD3
SIO3
P1/P2 Pin
P1.8
P1.10
P1.26
P1.41
P1.44
P2.21
P1.15
P1.16
P1.11
P1.12
P1.17
P1.14
P1.13
P1.19
P1.4
P1.3
P1.22
P1.23
P1.6
DS50002333A-page 26
 2015 Microchip Technology Inc.