EVB-LAN9252 Datasheet, PDF (19/55 Pages) Microchip Technology – EVB-LAN9252-HBI-SPI-SQI-GPIO EtherCAT® HBI/SPI+GPIO

Board Details & Configuration
2.4.3 EEPROM Switch
The EVB-LAN9252-HBI-SPI-SQI-GPIO utilizes 0x50 (7-bit) I²C slave addressing. The
SW3 switch can be used to select the A0, A1, and A2 address bits, as shown in
Figure 2-2 and Table 2-11. The eighth bit of the slave address determines if the master
device wants to read or write to the EEPROM (24FC512).
FIGURE 2-2:
SLAVE ADDRESS ALLOCATION
Start
Read/Write
1 0 1 0 A2 A1 A0 R/W A
Slave Address
TABLE 2-11: EEPROM SWITCH
Switch
Description
Settings
SW3
I2C EEPROM address selection switch ON for logic 0 (default)
(A0, A1, A2). See Figure 2-2.
OFF for logic 1
2.4.4 HBI/SPI+GPIO Selection
The EVB-LAN9252-HBI-SPI-SQI-GPIO supports two LAN9252 configurations:
• HBI Mode
• SPI + 16 GPIO Mode
The HBI or SPI+GPIO configuration is selected using the DPDT SW11 to SW21
switches. By default, HBI mode is selected.
TABLE 2-12: HBI/SPI+GPIO SWITCH CONFIGURATIONS
Switch
Description
Settings
SW11 to SW21
SW11 to SW21
Up
Down
HBI Mode (Default)
SPI+GPIO Mode
FIGURE 2-3:
SW11-SW21 HBI/SPI+GPIO MODE SELECTION
HBI Mode
SPI+GPIO Mode
2.4.4.1 HBI MODE SELECTION
The LAN9252 supports six HBI modes. These six HBI modes (Multiplexed Modes and
Indexed Modes) can be selected using the SPST switches (P/N: 450301014042-Wurth
Electronics) SW5 through SW9 and SW22 through SW25. Through the switches the
LAN9252 HBI signals are connected to the SoC.
Note: For switch P/N: 450301014042, pin 1 is at the middle of the switch. To short
1-2, knob position must be in the 1-3 position, and vice versa.
 2015 Microchip Technology Inc.
DS50002333A-page 19