EVB-LAN9252 Datasheet, PDF (25/55 Pages) Microchip Technology – EVB-LAN9252-HBI-SPI-SQI-GPIO EtherCAT® HBI/SPI+GPIO

Board Details & Configuration
TABLE 2-21: ID SELECT SIGNALS
ID Selection Signal
Signal Name
ID0
ID0_SELECT_RB0
ID1
ID_SELECT_RB1
ID2
ID_SELECT_RB2
ID3
ID_SELECT_RB3
ID4
ID_SELECT_RB4
ID5
ID_SELECT_RB5
ID6
ID_SELECT_RB8
ID7
ID_SELECT_RB9
ID8
ID_SELECT_RB10
ID9
ID_SELECT_RB11
ID10
ID_SELECT_RB12
ID11
ID12
ID13
ID14
ID15
ID_SELECT_RB13
ID_SELECT_RC1
ID_SELECT_RC2
ID_SELECT_RC3
ID_SELECT_RC4
PIC Pin Number
25
24
23
22
21
20
32
33
34
35
41
42
6
7
8
9
Switch Pin Number
SW7.1
SW7.2
SW7.3
SW7.4
SW7.5
SW7.6
SW7.7
SW7.8
SW8.1
SW8.2
SW8.3
SW8.4
SW8.5
SW8.6
SW8.7
SW8.8
2.5 DIG-IO & SPI+16GPIO SIGNALS ON P1 AND P2 HEADERS
2.5.1 DIG-IO on P1 and P2 Headers (up to 16 bits supported)
The LAN9252 supports a DIG-IO mode, where these signals can be probed on the P1
and P2 headers. To enable DIG-IO mode, from the default state of the board, the SW26
switch must be changed to the PIM position (upward). The respective DIG-IO signal
mappings on the P1 and P2 headers are detailed in Table 2-22.
Note 1: In the default state, headers P1 and P2 are not assembled. These headers
can each be populated with a Molex 87758-4616.
2: The user must ensure the respective mode’s demo code is programmed
into EEPROM.
TABLE 2-22: DIG-IO MODE P1 & P2 HEADER SIGNALS
HBI Indexed
HBI Multiplexed
DIG-IO
RD/RD_WR
WR/ENB
CS
A4
A3
A2
RD/RD_WR
WR/ENB
CS
-
-
ALEHI
DIGIO15
DIGIO14
DIGIO13
DIGIO12
DIGIO11
DIGIO10
A1
ALELO
OE_EXT
A0/D15
AD15
DIGIO9
D14
AD14
DIGIO8
D13
AD13
D12
AD12
D11
AD11
DIGIO7
DIGIO6
DIGIO5
P1/P2 Pin
P1.8
P1.10
P1.26
P1.41
P1.44
P2.21
P1.7
P1.15
P1.16
P1.11
P1.12
P1.17
 2015 Microchip Technology Inc.
DS50002333A-page 25