DSPIC33FJ32GS406 Datasheet, PDF (257/416 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 17-1: QEIxCON: QEIx CONTROL REGISTER (x = 1 or 2) (CONTINUED)
bit 5
bit 4-3
bit 2
bit 1
bit 0
TQGATE: Timer Gated Time Accumulation Enable bit
1 = Timer gated time accumulation enabled
0 = Timer gated time accumulation disabled
TQCKPS<1:0>: Timer Input Clock Prescale Select bits⁽³⁾
11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
POSRES: Position Counter Reset Enable bit⁽⁴⁾
1 = Index Pulse resets Position Counter
0 = Index Pulse does not reset Position Counter
TQCS: Timer Clock Source Select bit
1 = External clock from pin QEAx (on the rising edge)
0 = Internal clock (TCY)
UPDN_SRC: Position Counter Direction Selection Control bit⁽⁵⁾
1 = QEBx pin state defines position counter direction
0 = Control/Status bit, UPDN (QEIxCON<11>), defines timer counter (POSxCNT) direction
Note 1: CNTERR flag only applies when QEIM<2:0> = ‘110’ or ‘100’.
2: Read-only bit when QEIM<2:0> = ‘1XX’. Read/write bit when QEIM<2:0> = ‘001’.
3: Prescaler utilized for 16-bit Timer mode only.
4: This bit applies only when QEIM<2:0> = 100 or 110.
5: When configured for QEI mode, this control bit is a ‘don’t care’.
 2009 Microchip Technology Inc.
Preliminary
DS70591B-page 257