PIC16F722 Datasheet, PDF(24/302 Page) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology

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PIC16F722 Datasheet, PDF (24/302 Pages) Microchip Technology – 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology

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PIC16F72X/PIC16LF72X

TABLE 2-1: PIC16F72X/PIC16LF72X SPECIAL FUNCTION REGISTER SUMMARY

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Page

Bank 0

00h(2)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

xxxx xxxx 31,40

01h

TMR0

Timer0 Module Register

xxxx xxxx 111,40

02h(2)

PCL

Program Counter (PC) Least Significant Byte

0000 0000 30,40

03h(2)

STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

0001 1xxx 27,40

04h(2)

FSR

Indirect Data Memory Address Pointer

xxxx xxxx 31,40

05h

PORTA

RA7

RA6

RA5

RA4

RA3

RA2

RA1

RA0 xxxx xxxx 54,40

06h

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0 xxxx xxxx 63,40

07h

08h(3)

09h

0Ah(1, 2)

0Bh(2)

PORTC

PORTD

PORTE

PCLATH

INTCON

RC7

RD7

â

â

GIE

RC6

RD6

â

â

PEIE

RC5

RD5

â

â

T0IE

RC4

RC3

RC2

RC1

RC0

RD4

â

RD3

RE3

RD2

RE2(3)

RD1

RE1(3)

RD0

RE0(3)

Write Buffer for the upper 5 bits of the Program Counter

INTE

RBIE

T0IF

INTF

RBIF

xxxx xxxx

xxxx xxxx

---- xxxx

---0 0000

0000 000x

73,40

80,40

85,40

30,40

46,40

0Ch

PIR1

TMR1GIF ADIF

RCIF

TXIF

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 49,40

0Dh

PIR2

â

â

â

â

â

â

â

CCP2IF ---- ---0 50,40

0Eh

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx 120,40

0Fh

TMR1H

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx 120,40

10h

T1CON

TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

â

TMR1ON 0000 00-0 124,40

11h

TMR2

Timer2 Module Register

0000 0000 127,40

12h

T2CON

â

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 128,40

13h

SSPBUF

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx 169,40

14h

SSPCON

WCOL SSPOV SSPEN

CKP

SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 186,40

15h

CCPR1L

Capture/Compare/PWM Register (LSB)

xxxx xxxx 137,40

16h

CCPR1H

Capture/Compare/PWM Register (MSB)

xxxx xxxx 137,40

17h

CCP1CON

â

â

DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 136,40

18h

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D 0000 000x 155,40

19h

TXREG

USART Transmit Data Register

0000 0000 154,40

1Ah

RCREG

USART Receive Data Register

0000 0000 152,40

1Bh

CCPR2L

Capture/Compare/PWM Register 2 (LSB)

xxxx xxxx 137,40

1Ch

CCPR2H

Capture/Compare/PWM Register 2 (MSB)

xxxx xxxx 137,40

1Dh

CCP2CON

â

â

DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 136,40

1Eh

ADRES

A/D Result Register

xxxx xxxx 105,41

1Fh

ADCON0

â

â

CHS3

CHS2

CHS1

CHS0 GO/DONE ADON --00 0000 104,41

Legend:

Note 1:

2:

3:

4:

5:

6:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as â0â, r = reserved.

Shaded locations are unimplemented, read as â0â.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are

transferred to the upper byte of the program counter.

These registers can be addressed from any bank.

These registers/bits are not implemented on PIC16F722/723/726/PIC16LF722/723/726 devices, read as â0â.

Accessible only when SSPM<3:0> = 1001.

Accessible only when SSPM<3:0> â 1001.

This bit is always â1â as RE3 is input only.

DS41341E-page 24

Â© 2009 Microchip Technology Inc.

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