MCP651_11 Datasheet, PDF (24/56 Pages) Microchip Technology – 50 MHz, 6 mA Op Amps with mCal

MCP651/2/4/5/9
When the V_CAL pin is left open, the internal resistor
divider generates a V_{CM_INT} of approximately V_DD/3,
which is near the center of the input common mode
voltage range. It is recommended that an external
capacitor from V_CAL to ground be added to improve
noise immunity.
When the V_CAL pin is driven by an external voltage
source, which is within its specified range, the op amp
will have its input offset voltage calibrated at that com-
mon mode input voltage. Make sure that V_CAL is within
its specified range.
It is possible to use an external resistor voltage divider
to modify V_{CM_INT}; see Figure 4-2. The internal circuitry
at the V_CAL pin looks like 100 kΩ tied to V_DD/3. The
parallel equivalent of R₁ and R₂ should be much
smaller than 100 kΩ to minimize differences in match-
ing and temperature drift between the internal and
external resistors. Again, make sure that V_CAL is within
its specified range.
V_DD
R₁
C₁
R₂
MCP65X
V_CAL
V_SS
FIGURE 4-2:
Resistors.
Setting V_CM with External
For instance, a design goal to set V_{CM_INT} = 0.1V when
V_DD = 2.5V could be met with: R₁ = 24.3 kΩ,
R₂ = 1.00 kΩ and C₁ = 100 nF. This will keep V_CAL
within its range for any V_DD, and should be close
enough to 0V for ground based applications.
4.2 Input
4.2.1 PHASE REVERSAL
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-41 shows an input voltage
exceeding both supplies with no phase inversion.
4.2.2
INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-3. This structure was chosen to
protect the input transistors, and to minimize input bias
current (I_B). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
V_SS. They also clamp any voltages that go too far
above V_DD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
V_DD
Bond
Pad
V_IN+
Bond
Pad
Input
Stage
Bond
Pad
V_IN–
V_SS
Bond
Pad
FIGURE 4-3:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Section 1.1
“Absolute Maximum Ratings †”). Figure 4-4 shows
the recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (V_IN+
and V_IN–) from going too far below ground, and the
resistors R₁ and R₂ limit the possible current drawn out
of the input pins. Diodes D₁ and D₂ prevent the input
pins (V_IN+ and V_IN–) from going too far above V_DD, and
dump any currents onto V_DD. When implemented as
shown, resistors R₁ and R₂ also limit the current
through D₁ and D₂.
V_DD
D₁
R₁
V₁
V₂
R₂
D₂
MCP65X
V_OUT
R₁
>
V_SS
–
(minimum expected
2 mA
V₁)
R₂
>
V_SS
–
(minimum expected
2 mA
V₂)
FIGURE 4-4:
Inputs.
Protecting the Analog
It is also possible to connect the diodes to the left of the
resistor R₁ and R₂. In this case, the currents through
the diodes D₁ and D₂ need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (V_IN+ and
V_IN–) should be very small.
DS22146B-page 24
© 2011 Microchip Technology Inc.