DM163006 Datasheet, PDF (238/320 Pages) Microchip Technology – High-Performance ROM-less Microcontrollers

PIC18C601/801
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Inclusive OR literal with WREG
[ label ] IORLW k
0 ≤ k ≤ 255
(WREG) .OR. k → WREG
N,Z
0000 1001 kkkk kkkk
The contents of WREG are OR’ed
with the eight bit literal 'k'. The result
is placed in WREG.
1
1
Q2
Read
literal ’k’
Q3
Process
Data
Q4
Write to
WREG
Example:
IORLW
35h
Before Instruction
WREG = 9Ah
N
=?
Z
=?
After Instruction
WREG =
N
=
Z
=
0BFh
1
0
IORWF
Inclusive OR WREG with f
Syntax:
[ label ] IORWF f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(WREG) .OR. (f) → dest
Status Affected: N,Z
Encoding:
0001 00da ffff ffff
Description:
Inclusive OR WREG with register
'f'. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is
placed back in register 'f' (default).
If ’a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ is 1, the Bank will be selected
as per the BSR value.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Read
register ’f’
Q3
Process
Data
Q4
Write to
destination
Example:
IORWF RESULT, W
Before Instruction
RESULT = 13h
WREG = 91h
N
=?
Z
=?
After Instruction
RESULT = 13h
WREG = 93h
N
=1
Z
=0
DS39541A-page 238
Advance Information
 2001 Microchip Technology Inc.