DM163006 Datasheet, PDF (235/320 Pages) Microchip Technology – High-Performance ROM-less Microcontrollers

PIC18C601/801
DECFSZ
Decrement f, skip if 0
Syntax:
[ label ] DECFSZ f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
skip if result = 0
Status Affected: None
Encoding:
0010 11da ffff ffff
Description:
The contents of register 'f' are decre-
mented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the result
is placed back in register 'f' (default).
If the result is 0, the next instruction,
which is already fetched, is dis-
carded, and a NOP is executed
instead, making it a two-cycle
instruction. If ’a’ is 0, the Access
Bank will be selected, overriding the
BSR value. If ’a’ is 1, the Bank will
be selected as per the BSR value.
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
DECFSZ
GOTO
CONTINUE
CNT
LOOP
Before Instruction
PC
= Address (HERE)
After Instruction
CNT =
If CNT =
PC =
If CNT ≠
PC =
CNT - 1
0;
Address (CONTINUE)
0;
Address (HERE+2)
DCFSNZ
Decrement f, skip if not 0
Syntax:
[label] DCFSNZ f [,d [,a]]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
(f) – 1 → dest,
skip if result ≠ 0
Status Affected: None
Encoding:
0100 11da ffff ffff
Description:
The contents of register 'f' are decre-
mented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the result
is placed back in register 'f' (default).
If the result is not 0, the next instruc-
tion, which is already fetched, is
discarded, and a NOP is executed
instead, making it a two-cycle
instruction. If ’a’ is 0, the Access
Bank will be selected, overriding the
BSR value. If ’a’ is 1, the Bank will
be selected as per the BSR value.
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
ZERO
NZERO
DCFSNZ TEMP
:
:
Before Instruction
TEMP
=?
After Instruction
TEMP
If TEMP
PC
If TEMP
PC
= TEMP - 1,
= 0;
= Address (ZERO)
≠ 0;
= Address (NZERO)
 2001 Microchip Technology Inc.
Advance Information
DS39541A-page 235