PIC16F87_13 Datasheet, PDF (222/230 Pages) Microchip Technology – 18/20/28-Pin Enhanced Flash MCUs with nanoWatt Technology

PIC16F87/88
STATUS Register
C Bit ........................................................................... 19
DC Bit ......................................................................... 19
IRP Bit ........................................................................ 19
PD Bit ................................................................. 19, 134
RP Bits ....................................................................... 19
TO Bit ................................................................. 19, 134
Z Bit ............................................................................ 19
Synchronous Master Reception
Associated Registers ............................................... 112
Synchronous Master Transmission
Associated Registers ............................................... 111
Synchronous Serial Port (SSP) .......................................... 89
Overview .................................................................... 89
SPI Mode ................................................................... 89
Synchronous Slave Reception
Associated Registers ............................................... 114
Synchronous Slave Transmission
Associated Registers ............................................... 113
T
T1CKPS0 Bit ...................................................................... 74
T1CKPS1 Bit ...................................................................... 74
T1CON Register ................................................................. 16
T1OSCEN Bit ..................................................................... 74
T1SYNC Bit ........................................................................ 74
T2CKPS0 Bit ...................................................................... 82
T2CKPS1 Bit ...................................................................... 82
T2CON Register ................................................................. 16
Tad ................................................................................... 120
Time-out Sequence .......................................................... 136
Timer0 ................................................................................ 69
Associated Registers ................................................. 71
Clock Source Edge Select (T0SE Bit) ........................ 20
Clock Source Select (T0CS Bit) ................................. 20
External Clock ............................................................ 70
Interrupt ...................................................................... 69
Operation ................................................................... 69
Overflow Enable (TMR0IE Bit) ................................... 21
Overflow Flag (TMR0IF Bit) ..................................... 142
Overflow Interrupt .................................................... 142
Prescaler .................................................................... 70
T0CKI ......................................................................... 70
Timer1 ................................................................................ 73
Associated Registers ................................................. 79
Capacitor Selection .................................................... 77
Counter Operation ..................................................... 75
Operation ................................................................... 73
Operation in Asynchronous Counter Mode ................ 76
Reading and Writing .......................................... 76
Operation in Synchronized Counter Mode ................. 75
Operation in Timer Mode ........................................... 75
Oscillator .................................................................... 77
Oscillator Layout Considerations ............................... 77
Prescaler .................................................................... 78
Resetting Timer1 Register Pair .................................. 78
Resetting Timer1 Using a CCP Trigger Output .......... 78
Use as a Real-Time Clock ......................................... 78
Timer2 ................................................................................ 81
Associated Registers ................................................. 82
Output ........................................................................ 81
Postscaler .................................................................. 81
Prescaler .................................................................... 81
Prescaler and Postscaler ........................................... 81
Timing Diagrams
A/D Conversion ........................................................ 191
Asynchronous Master Transmission ........................ 105
Asynchronous Master Transmission (Back to Back) 105
Asynchronous Reception ......................................... 106
Asynchronous Reception with Address Byte First ... 109
Asynchronous Reception with Address Detect ........ 109
AUSART Synchronous Receive (Master/Slave) ...... 189
AUSART Synchronous Transmission (Master/Slave) ...
189
Brown-out Reset ...................................................... 181
Capture/Compare/PWM (CCP1) ............................. 183
CLKO and I/O .......................................................... 180
External Clock .......................................................... 179
Fail-Safe Clock Monitor ........................................... 146
I²C Bus Data ............................................................ 187
I²C Bus Start/Stop Bits ............................................ 186
I²C Reception (7-Bit Address) ................................... 96
I²C Transmission (7-Bit Address) .............................. 96
Primary System Clock After Reset (EC, RC, INTRC) 50
Primary System Clock After Reset (HS, XT, LP) ....... 49
PWM Output .............................................................. 86
Reset, Watchdog Timer, Oscillator Start-up Timer and
Power-up Timer ............................................... 181
Slow Rise Time (MCLR Tied to Vdd Through RC Net-
work) ................................................................ 140
SPI Master Mode ....................................................... 93
SPI Master Mode (CKE = 0, SMP = 0) .................... 184
SPI Master Mode (CKE = 1, SMP = 1) .................... 184
SPI Slave Mode (CKE = 0) ................................ 93, 185
SPI Slave Mode (CKE = 1) ................................ 93, 185
Switching to SEC_RUN Mode ................................... 46
Synchronous Reception (Master Mode, SREN) ...... 113
Synchronous Transmission ..................................... 111
Synchronous Transmission (Through TXEN) .......... 111
Time-out Sequence on Power-up (MCLR Tied to Vdd
Through Pull-up Resistor) ................................ 139
Time-out Sequence on Power-up (MCLR Tied to Vdd
Through RC Network): Case 1 ........................ 139
Time-out Sequence on Power-up (MCLR Tied to Vdd
Through RC Network): Case 2 ........................ 139
Timer0 and Timer1 External Clock .......................... 182
Timer1 Incrementing Edge ........................................ 75
Transition Between SEC_RUN/RC_RUN and Primary
Clock .................................................................. 48
Two-Speed Start-up Mode ....................................... 145
Wake-up from Sleep via Interrupt ............................ 148
XT, HS, LP, EC and EXTRC to RC_RUN Mode ........ 45
Timing Parameter Symbology ......................................... 178
Timing Requirements
A/D Conversion ........................................................ 191
AUSART Synchronous Receive .............................. 189
AUSART Synchronous Transmission ...................... 189
Capture/Compare/PWM (CCP1) ............................. 183
CLKO and I/O .......................................................... 180
External Clock .......................................................... 179
I²C Bus Data ............................................................ 188
I²C Bus Start/Stop Bits ............................................ 187
Reset, Watchdog Timer, Oscillator Start-up Timer, Pow-
er-up Timer and Brown-out Reset ................... 181
SPI Mode ................................................................. 186
Timer0 and Timer1 External Clock .......................... 182
TMR0 Register ............................................................. 16, 18
TMR1CS Bit ....................................................................... 74
TMR1H Register ................................................................ 16
DS30487D-page 222
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