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PIC16F87_13 Datasheet, PDF (20/230 Pages) Microchip Technology – 18/20/28-Pin Enhanced Flash MCUs with nanoWatt Technology | |||
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PIC16F87/88
2.2.2.4 PIE1 Register
This register contains the individual enable bits for the
peripheral interrupts.
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
REGISTER 2-4:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS 8Ch)
U-0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
â
ADIE(1)
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE
bit 7
bit 0
bit 7 Unimplemented: Read as â0â
bit 6 ADIE: A/D Converter Interrupt Enable bit(1)
1 = Enabled
0 = Disabled
Note 1: This bit is only implemented on the PIC16F88. The bit will read â0â on the PIC16F87.
bit 5 RCIE: AUSART Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4 TXIE: AUSART Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3 SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
â1â = Bit is set
U = Unimplemented bit, read as â0â
â0â = Bit is cleared x = Bit is unknown
DS30487D-page 20
ï£ 2002-2013 Microchip Technology Inc.
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