RFHCS362G_11 Datasheet, PDF (22/54 Pages) Microchip Technology – KEELOQ® Code Hopping Encoder with UHF ASK/FSK Transmitter

rfHCS362G/362F
TABLE 4-3:
Bit
Address
0
1
2
...
8
9
10
11
12
CONFIG_1
Field
DISC_0
DISC_1
DISC_2
...
DISC_8
DISC_9
OVR_0
OVR_1
XSER
13
SEEDC
Description
Discrimination bits
DISC[9:0]
Values
Overflow
OVR[1:0]
Extended Serial Number
Seed Control
0 - Disable
1 - Enable
0 = Seed transmission on:
S[3210] = 0001 (delay 1.6 s)
S[3210] = 0101 (immediate)
1 = Seed transmission on:
S[3210] = 0011 (delay 3.2 s)
S[3210] = 1001 (immediate)
14
SEED_0
Seed options
15
SEED_1
4.5.5 GUARD
The Guard time between code words can be set to 0
ms, 6.4 ms, 25.6 ms and 76.8 ms. If during a series of
code words, the output changes from Hopping Code to
Seed the Guard time will increase by 3 x TE.
4.5.6 TIMOUT[0..1]
The transmission time-out can be set to 0.8 s, 3.2 s,
25.6 s or no time-out. After the time-out period, the
encoder will stop transmission and enter a low power
Shutdown mode.
4.5.7 DISC[0..9]
The discrimination bits are used to validate the
decrypted code word. The discrimination value is typi-
cally programmed with the 10 Least Significant bits of
the serial number or a fixed value.
4.5.8 OVR[0..1]
The automatically incrementing synchronization coun-
ter is at the core of generating the varying code. Since
the counter is limited to 16 bits, it overflows after 65536
increments, after which the code hopping sequence
repeats. In practice, this allows 20+ operations per day
for ten years before repeating the sequence. In addi-
tion, two overflow bits allow the sequence to be
extended further. The feature is enabled by setting to
00 - No Seed
01 - Limited Seed (Permanent and Delayed)
10 - Permanent and Delayed Seed
11 - Permanent Seed only
logical “1” the two overflow bits OVL0 and OVL1. The
overflow bits form part of the encrypted transmission,
and therefore can be examined by receiver firmware.
Table 4-4 shows how the overflow bits act when they
are set to one during initial device configuration.
TABLE 4-4:
Sync. Counter
No overflow
0-FFFFH
First overflow
2nd 0-FFFFH
Second overflow
Third 0-FFFFH
Subsequent overflows
OVL0
1
0
0
0
OVL1
1
1
0
0
As can be seen from the table, the counter is effectively
extended by one bit, that is OVL0. In addition, OVL1
provides indication of the second counter overflow.
After the second overflow, OVL0 and OVL1 remain
zero, providing permanent evidence of the first and
second overflow events.
DS41189B-page 22
© 2011 Microchip Technology Inc.