PIC18F67J50-I Datasheet, PDF (2/16 Pages) Microchip Technology – PIC18F87J50 Family Silicon Errata and Data Sheet Clarification

PIC18F87J50 FAMILY
TABLE 2: SILICON ISSUE SUMMARY
Module
Feature
Item
Number
Issue Summary
Affected Revisions⁽¹⁾
A2
A3
A4
MSSP
I²C™ Slave
1.
With I²C slave reception, need to read data
promptly
X
X
X
MSSP
I²C Master
2.
With I²C Master mode, narrow clock width
upon slave clock stretch
X
X
X
EUSART Interrupts
3.
If interrupts are enabled, 2 TCY delay needed
after re-enabling the module
X
X
X
MSSP
SPI Master
mode
4.
SPI master, write collision for FOSC/64 and
Timer2/2
X
X
X
PORTH RH0, RH1
5.
In certain cases, PMP can override RH0 and
RH1
X
X
X
Note 1: Only those issues indicated in the last column apply to the current silicon revision.
DS80481A-page 2
© 2009 Microchip Technology Inc.