USB3320 Datasheet, PDF (19/70 Pages) Microchip Technology – Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver

USB3320
TABLE 5-1:
DP/DM TERMINATION VS. SIGNALING MODE (CONTINUED)
ULPI Register Settings
USB3320 Termination Resistor
Settings
Signaling Mode
Peripheral Test J/Test K
00b 0b 10b 0b 0b 0b 0b 0b 0b 1b
OTG device, Peripheral Chirp
00b 1b 10b 0b 1b 1b 0b 0b 1b 0b
OTG device, Peripheral HS
00b 0b 00b 0b 1b 0b 0b 0b 1b 1b
OTG device, Peripheral FS
01b 1b 00b 0b 1b 1b 0b 0b 1b 0b
OTG device, Peripheral HS/FS Suspend
01b 1b 00b 0b 1b 1b 0b 0b 1b 0b
OTG device, Peripheral HS/FS Resume
01b 1b 10b 0b 1b 1b 0b 0b 1b 0b
OTG device, Peripheral Test J/Test K
00b 0b 10b 0b 1b 0b 0b 0b 1b 1b
Any combination not defined above Note 5-
1
0b 0b 0b 0b 0b
Note 1: This is the same as Table 40, Section 4.4 of the ULPI 1.1 specification.
2: USB3320 does not support operation as an upstream hub port. See Section 6.2.4.3, "UTMI+ Level 3".
Note 5-1 The transceiver operation is not ensured in a combination that is not defined.
The USB3320 uses the 27% resistor ECN resistor tolerances. The resistor values are shown in Table 4-5.
5.3 Bias Generator
This block consists of an internal bandgap reference circuit used for generating the driver current and the biasing of the
analog circuits. This block requires an external 8.06KΩ, 1% tolerance, reference resistor connected from RBIAS to
ground. This resistor should be placed as close as possible to the USB3320 to minimize the trace length. The nominal
voltage at RBIAS is 0.8V +/- 10% and therefore the resistor will dissipate approximately 80μW of power.
5.4 Integrated Low Jitter PLL
The USB3320 uses an integrated low jitter phase locked loop (PLL) to provide a clean 480MHz clock required for HS
USB signal quality. This clock is used by the transceiver during both transmit and receive. The USB3320 PLL requires
an accurate frequency reference to be driven on the REFCLK pin.
5.4.1 REFCLK MODE SELECTION
The USB3320 is designed to operate in one of two available modes as shown in Table 5-2. In the first mode, a 60MHz
ULPI clock is driven on the REFCLK pin as described in Section 5.4.1.1. In the second mode, the USB3320 generates
the ULPI clock as described in Section 5.4.1.2. When using the second mode, the frequency of the reference clock is
configured by REFSEL[2], REFSEL[1] and REFSEL[0] as described in Section 5.10.
TABLE 5-2: REFCLK MODES
Mode
ULPI Input Clock Mode
ULPI Output Clock
Mode
REFCLK
Frequency
60Mhz
Table 5-10
ULPI Clock Description
Sourced by Link, driven on the REFCLK pin
Sourced by USB3320 at the CLKOUT pin
During start-up, the USB3320 monitors the CLKOUT pin to determine which mode has been configured as described
in Section 5.4.1.1.
 2014-2015 Microchip Technology Inc.
DS00001792B-page 19